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219e788dc6
This prevents the machine verifier from complaining about uses of an undefined physical register. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192364 91177308-0d34-0410-b5e6-96231b3b80d8
85 lines
2.4 KiB
C++
85 lines
2.4 KiB
C++
//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SIRegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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using namespace llvm;
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SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm)
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: AMDGPURegisterInfo(tm),
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TM(tm)
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{ }
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BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(AMDGPU::EXEC);
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return Reserved;
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}
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unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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return RC->getNumRegs();
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}
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const TargetRegisterClass *
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SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
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switch (rc->getID()) {
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case AMDGPU::GPRF32RegClassID:
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return &AMDGPU::VReg_32RegClass;
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default: return rc;
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}
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}
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const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
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MVT VT) const {
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switch(VT.SimpleTy) {
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default:
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case MVT::i32: return &AMDGPU::VReg_32RegClass;
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}
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}
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const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
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assert(!TargetRegisterInfo::isVirtualRegister(Reg));
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const TargetRegisterClass *BaseClasses[] = {
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&AMDGPU::VReg_32RegClass,
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&AMDGPU::SReg_32RegClass,
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&AMDGPU::VReg_64RegClass,
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&AMDGPU::SReg_64RegClass,
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&AMDGPU::SReg_128RegClass,
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&AMDGPU::SReg_256RegClass
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};
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for (unsigned i = 0, e = sizeof(BaseClasses) /
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sizeof(const TargetRegisterClass*); i != e; ++i) {
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if (BaseClasses[i]->contains(Reg)) {
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return BaseClasses[i];
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}
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}
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return NULL;
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}
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bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
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if (!RC) {
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return false;
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}
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return RC == &AMDGPU::SReg_32RegClass ||
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RC == &AMDGPU::SReg_64RegClass ||
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RC == &AMDGPU::SReg_128RegClass ||
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RC == &AMDGPU::SReg_256RegClass ||
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RC == &AMDGPU::SReg_512RegClass;
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}
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