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a787066317
This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234381 91177308-0d34-0410-b5e6-96231b3b80d8
36 lines
1.1 KiB
ArmAsm
36 lines
1.1 KiB
ArmAsm
// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s
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//===----------------------------------------------------------------------===//
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// Generic checks
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//===----------------------------------------------------------------------===//
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v_mul_i32_i24 v1, v2, 100
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// CHECK: error: invalid operand for instruction
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//===----------------------------------------------------------------------===//
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// _e32 checks
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//===----------------------------------------------------------------------===//
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// Immediate src1
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v_mul_i32_i24_e32 v1, v2, 100
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// CHECK: error: invalid operand for instruction
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// sgpr src1
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v_mul_i32_i24_e32 v1, v2, s3
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// CHECK: error: invalid operand for instruction
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//===----------------------------------------------------------------------===//
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// _e64 checks
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//===----------------------------------------------------------------------===//
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// Immediate src0
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v_mul_i32_i24_e64 v1, 100, v3
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// CHECK: error: invalid operand for instruction
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// Immediate src1
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v_mul_i32_i24_e64 v1, v2, 100
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// CHECK: error: invalid operand for instruction
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// TODO: Constant bus restrictions
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