llvm-6502/lib/Target/CellSPU
Daniel Dunbar b8ebca83f4 build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies.
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144444 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 02:10:57 +00:00
..
MCTargetDesc build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies. 2011-11-12 02:10:57 +00:00
TargetInfo build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies. 2011-11-12 02:10:57 +00:00
CellSDKIntrinsics.td do some serious surgery on CellSPU to get it back into a world 2010-03-15 05:53:47 +00:00
CMakeLists.txt build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just 2011-11-04 19:04:23 +00:00
LLVMBuild.txt LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler. 2011-11-11 00:23:56 +00:00
Makefile Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
README.txt Allow sign-extending of i8 and i16 to i128 on SPU. 2011-01-20 15:49:06 +00:00
SPU64InstrInfo.td Fix a ton of comment typos found by codespell. Patch by 2011-04-15 05:18:47 +00:00
SPU128InstrInfo.td
SPU.h Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
SPU.td
SPUAsmPrinter.cpp Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
SPUCallingConv.td Remove all traces of v2[i,f]32 on SPU. 2010-08-18 10:04:39 +00:00
SPUFrameLowering.cpp Don't insert branch hint lables that are never used. 2011-08-26 10:14:56 +00:00
SPUFrameLowering.h Don't insert branch hint lables that are never used. 2011-08-26 10:14:56 +00:00
SPUHazardRecognizers.cpp Various bits of framework needed for precise machine-level selection 2010-12-24 05:03:26 +00:00
SPUHazardRecognizers.h Various bits of framework needed for precise machine-level selection 2010-12-24 05:03:26 +00:00
SPUInstrBuilder.h
SPUInstrFormats.td Add branch hinting for SPU. 2011-02-28 14:08:24 +00:00
SPUInstrInfo.cpp Fix a iterator out of bounds error, that triggers rarely. 2011-10-11 12:55:18 +00:00
SPUInstrInfo.h Hide the call to InitMCInstrInfo into tblgen generated ctor. 2011-07-01 17:57:27 +00:00
SPUInstrInfo.td Mark 'branch indirect' instruction as an indirect branch. 2011-10-13 11:40:03 +00:00
SPUISelDAGToDAG.cpp Added invariant field to the DAG.getLoad method and changed all calls. 2011-11-08 18:42:53 +00:00
SPUISelLowering.cpp Added invariant field to the DAG.getLoad method and changed all calls. 2011-11-08 18:42:53 +00:00
SPUISelLowering.h Add codegen support for vector select (in the IR this means a select 2011-09-06 19:07:46 +00:00
SPUMachineFunction.h Move per-function state out of TargetLowering subclasses and into 2010-04-17 14:41:14 +00:00
SPUMathInstr.td Remove all traces of v2[i,f]32 on SPU. 2010-08-18 10:04:39 +00:00
SPUNodes.td Flag -> Glue, the ongoing saga 2010-12-23 18:28:41 +00:00
SPUNopFiller.cpp Fix a thinko in 123226 that caused test failures on "other" platforms. 2011-01-11 11:27:56 +00:00
SPUOperands.td Don't feed 19 bit immediates to ILA. 2010-12-17 09:36:09 +00:00
SPURegisterInfo.cpp Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for 2011-07-18 22:29:13 +00:00
SPURegisterInfo.h Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down 2011-07-18 20:57:22 +00:00
SPURegisterInfo.td Use set operations instead of plain lists to enumerate register classes. 2011-06-15 23:28:14 +00:00
SPURegisterNames.h Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc 2011-06-27 18:32:37 +00:00
SPUSchedule.td Split up RotateShift itinerary in SPU. 2011-01-17 13:33:19 +00:00
SPUSelectionDAGInfo.cpp Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SPUSelectionDAGInfo.h Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SPUSubtarget.cpp Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
SPUSubtarget.h Compute feature bits at time of MCSubtargetInfo initialization. 2011-07-07 07:07:08 +00:00
SPUTargetMachine.cpp Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
SPUTargetMachine.h - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. 2011-07-20 07:51:56 +00:00

//===- README.txt - Notes for improving CellSPU-specific code gen ---------===//

This code was contributed by a team from the Computer Systems Research
Department in The Aerospace Corporation:

- Scott Michel (head bottle washer and much of the non-floating point
  instructions)
- Mark Thomas (floating point instructions)
- Michael AuYeung (intrinsics)
- Chandler Carruth (LLVM expertise)
- Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise)

Some minor fixes added by Kalle Raiskila.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR
OTHERWISE.  IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES
OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING
OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
OR PUNITIVE  DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
SUCH DAMAGES ARE FORESEEABLE.

---------------------------------------------------------------------------
--WARNING--:
--WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
--WARNING--:

If you are brave enough to try this code or help to hack on it, be sure
to add 'spu' to configure's --enable-targets option, e.g.:

        ./configure <your_configure_flags_here> \
           --enable-targets=x86,x86_64,powerpc,spu

---------------------------------------------------------------------------

TODO:
* Create a machine pass for performing dual-pipeline scheduling specifically
  for CellSPU, and insert branch prediction instructions as needed.

* i32 instructions:

  * i32 division (work-in-progress)

* i64 support (see i64operations.c test harness):

  * shifts and comparison operators: done
  * sign and zero extension: done
  * addition: done
  * subtraction: needed
  * multiplication: done

* i128 support:

  * zero extension, any extension: done
  * sign extension: done
  * arithmetic operators (add, sub, mul, div): needed
  * logical operations (and, or, shl, srl, sra, xor, nor, nand): needed

    * or: done

* f64 support

  * Comparison operators:
    SETOEQ              unimplemented
    SETOGT              unimplemented
    SETOGE              unimplemented
    SETOLT              unimplemented
    SETOLE              unimplemented
    SETONE              unimplemented
    SETO                done (lowered)
    SETUO               done (lowered)
    SETUEQ              unimplemented
    SETUGT              unimplemented
    SETUGE              unimplemented
    SETULT              unimplemented
    SETULE              unimplemented
    SETUNE              unimplemented

* LLVM vector suport

  * VSETCC needs to be implemented. It's pretty straightforward to code, but
    needs implementation.

* Intrinsics

  * spu.h instrinsics added but not tested. Need to have an operational
    llvm-spu-gcc in order to write a unit test harness.

===-------------------------------------------------------------------------===