Stepan Dyatkovskiy b52ba9f8a8 Issue: ... Stack is formed improperly for long structures passed as byval arguments for EABI mode. If we took AAPCS reference, we can found the next statements: A: "If the argument requires double-word alignment (8-byte), the NCRN (Next Core Register Number) is rounded up to the next even register number." (5.5 Parameter Passing, Stage C, C.3). B: "The alignment of an aggregate shall be the alignment of its most-aligned component." (4.3 Composite Types, 4.3.1 Aggregates). So if we have structure with doubles (9 double fields) and 3 Core unused registers (r1, r2, r3): caller should use r2 and r3 registers only. Currently r1,r2,r3 set is used, but it is invalid. Callee VA routine should also use r2 and r3 regs only. All is ok here. This behaviour is guessed by rounding up SP address with ADD+BFC operations. Fix: Main fix is in ARMTargetLowering::HandleByVal. If we detected AAPCS mode and 8 byte alignment, we waste odd registers then. P.S.: I also improved LDRB_POST_IMM regression test. Since ldrb instruction will not generated by current regression test after this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166018 91177308-0d34-0410-b5e6-96231b3b80d8		2012-10-16 07:16:47 +00:00
..
Mangler.h	whitespace	2012-10-09 01:56:07 +00:00
Target.td	comment	2012-09-14 06:18:52 +00:00
TargetCallingConv.h	Issue description:	2012-10-10 11:37:36 +00:00
TargetCallingConv.td	Add TableGen support for callee saved registers.	2012-01-17 22:46:58 +00:00
TargetELFWriterInfo.h	[Hexagon] Clean up Hexagon ELF definition.	2012-05-17 16:46:46 +00:00
TargetFrameLowering.h	Prune some includes and forward declarations.	2012-03-25 18:09:44 +00:00
TargetInstrInfo.h	misched: Use the TargetSchedModel interface wherever possible.	2012-10-10 05:43:09 +00:00
TargetIntrinsicInfo.h	Mark unimplemented copy constructors and copy assignment operators as LLVM_DELETED_FUNCTION.	2012-09-17 06:59:23 +00:00
TargetItinerary.td	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
TargetJITInfo.h	Prune some includes and forward declarations.	2012-03-25 18:09:44 +00:00
TargetLibraryInfo.h	Make MemoryBuiltins aware of TargetLibraryInfo.	2012-08-29 15:32:21 +00:00
TargetLowering.h	Issue:	2012-10-16 07:16:47 +00:00
TargetLoweringObjectFile.h	Mark unimplemented copy constructors and copy assignment operators as LLVM_DELETED_FUNCTION.	2012-09-17 06:59:23 +00:00
TargetMachine.h	Add a new interface to allow IR-level passes to access codegen-specific information.	2012-10-10 22:04:55 +00:00
TargetOpcodes.h	Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be	2012-09-06 09:17:37 +00:00
TargetOptions.h	Add support for the --param ssp-buffer-size= driver option.	2012-08-21 16:15:24 +00:00
TargetRegisterInfo.h	Add TRI::getSubRegIndexLaneMask().	2012-09-11 16:34:08 +00:00
TargetSchedule.td	Added instregex support to TableGen subtarget emitter.	2012-10-03 23:06:32 +00:00
TargetSelectionDAG.td	Remove extra MayLoad/MayStore flags from atomic_load/store.	2012-08-28 03:11:32 +00:00
TargetSelectionDAGInfo.h	Move TargetData to DataLayout.	2012-10-08 16:38:25 +00:00
TargetSubtargetInfo.h	misched: remove the unused getSpecialAddressLatency hook.	2012-10-08 18:54:00 +00:00
TargetTransformImpl.h	Shuffle the virtual destructor down to the base. This should actually pacify	2012-10-12 04:28:25 +00:00