Alex Lorenz 78bc2545c9 MIR Serialization: Serialize the 'dead' register machine operand flag. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241624 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-07 20:34:53 +00:00
..
AArch64	Add CHECK lines to test case	2015-07-07 19:26:31 +00:00
AMDGPU	AMDGPU/SI: Add debugging subtarget feature for DS offsets	2015-07-06 16:01:58 +00:00
ARM	Fix test case to unbreak build.	2015-07-07 14:45:12 +00:00
BPF
CPP
Generic	llc: Add a 'run-pass' option.	2015-07-06 17:44:26 +00:00
Hexagon
Inputs
Mips
MIR	MIR Serialization: Serialize the 'dead' register machine operand flag.	2015-07-07 20:34:53 +00:00
MSP430
NVPTX	[NVPTX] expand extload/truncstore for vectors of floats	2015-07-01 21:32:42 +00:00
PowerPC	Add missing builtins to the PPC back end for ABI compliance (vol. 2)	2015-07-05 06:03:51 +00:00
SPARC
SystemZ
Thumb
Thumb2
WebAssembly	[WebAssembly] Create a CodeGen unittest directory.	2015-07-06 23:14:57 +00:00
WinEH	[WinEH] Add some test cases I forgot to add to previous commits	2015-07-06 21:13:53 +00:00
X86	[X86][AVX] Add support for shuffle decoding of vperm2f128/vperm2i128 with zero'd lanes	2015-07-06 22:46:46 +00:00
XCore