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llvm-6502/test/CodeGen/X86/promote-assert-zext.ll
Dan Gohman 400f75cb5e Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. It
needs to demand the high bits because it's asserting that they're zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105406 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 20:21:33 +00:00

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693 B
LLVM

; RUN: llc < %s | FileCheck %s
; rdar://8051990
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin11"
; ISel doesn't yet know how to eliminate this extra zero-extend. But until
; it knows how to do so safely, it shouldn;t eliminate it.
; CHECK: movzbl (%rdi), %eax
; CHECK: movzwl %ax, %eax
define i64 @_ZL5matchPKtPKhiR9MatchData(i8* %tmp13) nounwind {
entry:
%tmp14 = load i8* %tmp13, align 1
%tmp17 = zext i8 %tmp14 to i16
br label %bb341
bb341:
%tmp18 = add i16 %tmp17, -1
%tmp23 = sext i16 %tmp18 to i64
ret i64 %tmp23
}