Suyog Sarda 4bfc4f2e8c Revert 224119 "This patch recognizes (+ (+ v0, v1) (+ v2, v3)), reorders them for bundling into vector of loads, ... and vectorizes it." This was re-ordering floating point data types resulting in mismatch in output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224424 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-17 10:34:27 +00:00
..
AArch64	Revert 224119 "This patch recognizes (+ (+ v0, v1) (+ v2, v3)), reorders them for bundling into vector of loads,	2014-12-17 10:34:27 +00:00
ARM	Preserve IR flags (nsw, nuw, exact, fast-math) in SLP vectorizer (PR20802).	2014-09-03 17:40:30 +00:00
R600
X86	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
XCore