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17200e3bb3
This will allow us to use a single MachineInstr to represent instructions which behave the same but have different encodings on some subtargets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209028 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.2 KiB
C++
49 lines
1.2 KiB
C++
//===- AMDGPUMCInstLower.h MachineInstr Lowering Interface ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPU_MCINSTLOWER_H
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#define AMDGPU_MCINSTLOWER_H
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namespace llvm {
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class AMDGPUSubtarget;
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class MCInst;
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class MCContext;
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class MachineInstr;
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class AMDGPUMCInstLower {
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// This must be kept in sync with the SISubtarget class in SIInstrInfo.td
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enum SISubtarget {
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SI = 0
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};
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MCContext &Ctx;
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const AMDGPUSubtarget &ST;
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/// Convert a member of the AMDGPUSubtarget::Generation enum to the
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/// SISubtarget enum.
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enum SISubtarget AMDGPUSubtargetToSISubtarget(unsigned Gen) const;
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/// Get the MC opcode for this MachineInstr.
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unsigned getMCOpcode(unsigned MIOpcode) const;
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public:
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AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &ST);
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/// \brief Lower a MachineInstr to an MCInst
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void lower(const MachineInstr *MI, MCInst &OutMI) const;
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};
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} // End namespace llvm
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#endif //AMDGPU_MCINSTLOWER_H
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