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https://github.com/c64scene-ar/llvm-6502.git
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9b22626068
The register spiller assumes that only one new instruction is created when spilling and restoring registers, so we need to emit pseudo instructions for vector register spills and lower them after register allocation. v2: - Fix calculation of lane index - Extend VGPR liveness to end of program. v3: - Use SIMM16 field of S_NOP to specify multiple NOPs. https://bugs.freedesktop.org/show_bug.cgi?id=75005 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207843 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
2.6 KiB
C++
77 lines
2.6 KiB
C++
//===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for SIRegisterInfo
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//
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//===----------------------------------------------------------------------===//
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#ifndef SIREGISTERINFO_H_
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#define SIREGISTERINFO_H_
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#include "AMDGPURegisterInfo.h"
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namespace llvm {
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class AMDGPUTargetMachine;
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struct SIRegisterInfo : public AMDGPURegisterInfo {
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AMDGPUTargetMachine &TM;
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SIRegisterInfo(AMDGPUTargetMachine &tm);
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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/// \param RC is an AMDIL reg class.
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///
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/// \returns the SI register class that is equivalent to \p RC.
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const TargetRegisterClass *
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getISARegClass(const TargetRegisterClass *RC) const override;
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/// \brief get the register class of the specified type to use in the
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/// CFGStructurizer
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const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
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unsigned getHWRegIndex(unsigned Reg) const override;
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/// \brief Return the 'base' register class for this register.
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/// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.
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const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
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/// \returns true if this class contains only SGPR registers
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bool isSGPRClass(const TargetRegisterClass *RC) const;
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/// \returns true if this class contains VGPR registers.
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bool hasVGPRs(const TargetRegisterClass *RC) const;
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/// \returns A VGPR reg class with the same width as \p SRC
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const TargetRegisterClass *getEquivalentVGPRClass(
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const TargetRegisterClass *SRC) const;
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/// \returns The register class that is used for a sub-register of \p RC for
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/// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
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/// be returned.
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const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
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unsigned SubIdx) const;
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/// \p Channel This is the register channel (e.g. a value from 0-16), not the
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/// SubReg index.
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/// \returns The sub-register of Reg that is in Channel.
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unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
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unsigned Channel) const;
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};
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} // End namespace llvm
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#endif // SIREGISTERINFO_H_
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