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https://github.com/c64scene-ar/llvm-6502.git
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badb137729
The previous situation where ATOMIC_LOAD_WHATEVER nodes were expanded at MachineInstr emission time had grown to be extremely large and involved, to account for the subtly different code needed for the various flavours (8/16/32/64 bit, cmpxchg/add/minmax). Moving this transformation into the IR clears up the code substantially, and makes future optimisations much easier: 1. an atomicrmw followed by using the *new* value can be more efficient. As an IR pass, simple CSE could handle this efficiently. 2. Making use of cmpxchg success/failure orderings only has to be done in one (simpler) place. 3. The common "cmpxchg; did we store?" idiom can be exposed to optimisation. I intend to gradually improve this situation within the ARM backend and make sure there are no hidden issues before moving the code out into CodeGen to be shared with (at least ARM64/AArch64, though I think PPC & Mips could benefit too). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205525 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
1.9 KiB
C++
60 lines
1.9 KiB
C++
//===-- ARM.h - Top-level interface for ARM representation ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// ARM back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TARGET_ARM_H
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#define TARGET_ARM_H
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#include "llvm/Support/CodeGen.h"
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namespace llvm {
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class ARMAsmPrinter;
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class ARMBaseTargetMachine;
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class FunctionPass;
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class ImmutablePass;
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class JITCodeEmitter;
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class MachineInstr;
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class MCInst;
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class TargetLowering;
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class TargetMachine;
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FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
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JITCodeEmitter &JCE);
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FunctionPass *createA15SDOptimizerPass();
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FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
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FunctionPass *createARMExpandPseudoPass();
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FunctionPass *createARMGlobalBaseRegPass();
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FunctionPass *createARMGlobalMergePass(const TargetLowering* tli);
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FunctionPass *createARMConstantIslandPass();
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FunctionPass *createMLxExpansionPass();
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FunctionPass *createThumb2ITBlockPass();
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FunctionPass *createARMOptimizeBarriersPass();
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FunctionPass *createThumb2SizeReductionPass();
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/// \brief Creates an ARM-specific Target Transformation Info pass.
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ImmutablePass *createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM);
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FunctionPass *createARMAtomicExpandPass(const TargetMachine *TM);
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void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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ARMAsmPrinter &AP);
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} // end namespace llvm;
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#endif
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