Vincent Lejeune cf1f4c7dd1 R600: improve dump of S_WAITCNT ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192557 91177308-0d34-0410-b5e6-96231b3b80d8		2013-10-13 17:56:28 +00:00
..
AArch64	Implement aarch64 neon instruction set AdvSIMD (copy).	2013-10-11 02:33:55 +00:00
ARM	Remove kill flags after if conversion if necessary	2013-10-11 19:04:37 +00:00
CPP
Generic	Change objectsize intrinsic to accept different address spaces.	2013-10-07 18:06:48 +00:00
Hexagon	TBAA: remove !tbaa from testing cases when they are not needed.	2013-09-30 18:17:35 +00:00
Inputs	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
Mips	For Mips16, start to consolidate all forms of 32 bit literal loading so that	2013-10-12 02:19:08 +00:00
MSP430
NVPTX	[NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc	2013-10-11 12:39:39 +00:00
PowerPC	TBAA: update tbaa format from scalar format to struct-path aware format.	2013-09-30 18:17:55 +00:00
R600	R600: improve dump of S_WAITCNT	2013-10-13 17:56:28 +00:00
SPARC	[Sparc] Disable tail call optimization for sparc64.	2013-10-09 12:50:39 +00:00
SystemZ	[SystemZ] Add comparisons of high words and memory	2013-10-01 15:00:44 +00:00
Thumb	ARM: Use "dmb sy" for barriers on M-class CPUs	2013-08-28 14:39:19 +00:00
Thumb2	Fix spelling intruction -> instruction.	2013-09-28 11:46:15 +00:00
X86	Force a CPU on test so it doesn't depend on microarchitectural scheduling decisions.	2013-10-12 11:17:12 +00:00
XCore	XCore target fix bug in emitArrayBound() causing segmentation fault	2013-10-11 10:27:13 +00:00