llvm-6502/test/CodeGen
Andrew Trick 178f7d08a4 MISched: Add SchedDFSResult to ScheduleDAGMI to formalize the
interface and allow other strategies to select it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 04:01:04 +00:00
..
ARM Remove some register allocation order dependencies. 2013-01-19 00:03:32 +00:00
CPP
Generic For inline asm: 2013-01-11 18:12:39 +00:00
Hexagon Add indexed load/store instructions for offset validation check. 2013-01-17 18:42:37 +00:00
MBlaze
Mips [mips] Set flag neverHasSideEffects flag on some of the floating point instructions. 2013-01-25 00:20:39 +00:00
MSP430 Add support for varargs functions for msp430. 2012-11-21 17:28:27 +00:00
NVPTX [NVPTX] Fix crash with unnamed struct arguments 2012-12-05 20:50:28 +00:00
PowerPC Restore reverted test case, this time with REQUIRES: asserts 2013-01-17 19:46:51 +00:00
R600 DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes 2013-01-02 22:13:01 +00:00
SI Add R600 backend 2012-12-11 21:25:42 +00:00
SPARC Use TargetTransformInfo to control switch-to-lookup table transformation 2012-10-30 11:23:25 +00:00
Thumb Use the 'count' attribute to calculate the upper bound of an array. 2012-12-04 21:34:03 +00:00
Thumb2 Remove some register allocation order dependencies. 2013-01-19 00:03:32 +00:00
X86 MISched: Add SchedDFSResult to ScheduleDAGMI to formalize the 2013-01-25 04:01:04 +00:00
XCore Fix handling of aliases to functions. 2012-11-16 21:12:38 +00:00