Richard Osborne bb057453db Add checkevent intrinsic to check if any resources owned by the current thread ...

can event.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127741 91177308-0d34-0410-b5e6-96231b3b80d8

2011-03-16 18:34:00 +00:00

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2008-11-17-Shl64.ll

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2009-01-08-Crash.ll

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2009-01-14-Remat-Crash.ll

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2009-03-27-v2f64-param.ll

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2009-07-15-store192.ll

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2010-02-25-LSR-Crash.ll

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2010-04-07-DbgValueOtherTargets.ll

If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.

2010-12-06 22:39:26 +00:00

2011-01-31-DAGCombineBug.ll

Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.

2011-01-31 17:41:44 +00:00

addsub64.ll

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ashr.ll

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basictest.ll

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bigstructret.ll

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bitrev.ll

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constants.ll

Be nice to Xcore and the XMOS assembler and avoid quoting section names

2011-03-04 20:03:14 +00:00

cos.ll

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dg.exp

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events.ll

Add checkevent intrinsic to check if any resources owned by the current thread

2011-03-16 18:34:00 +00:00

exp2.ll

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exp.ll

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fneg.ll

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getid.ll

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globals.ll

Be nice to Xcore and the XMOS assembler and avoid quoting section names

2011-03-04 20:03:14 +00:00

indirectbr.ll

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ladd_lsub_combine.ll

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load.ll

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log2.ll

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log10.ll

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log.ll

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mul64.ll

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pow.ll

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powi.ll

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private.ll

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ps-intrinsics.ll

Add XCore intrinsics for getps, setps, setsr and clrsr.

2011-03-15 13:45:47 +00:00

resources.ll

Add XCore intrinsic for eeu instruction.

2011-02-24 13:39:18 +00:00

scavenging.ll

On the XCore the scavenging slot should be closest to the SP.

2011-03-15 15:10:11 +00:00

sext.ll

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sin.ll

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sqrt.ll

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sr-intrinsics.ll

Add XCore intrinsics for getps, setps, setsr and clrsr.

2011-03-15 13:45:47 +00:00

store.ll

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switch_long.ll

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switch.ll

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tls.ll

Be nice to Xcore and the XMOS assembler and avoid quoting section names

2011-03-04 20:03:14 +00:00

trampoline.ll

Fix mistyped CHECK lines.

2011-03-09 22:07:31 +00:00

trap.ll

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unaligned_load.ll

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unaligned_store_combine.ll

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unaligned_store.ll

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