mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-21 00:32:23 +00:00
ba51ae6864
Our register allocation has become better recently, it seems, and is now starting to generate cross-block copies into inflated register classes. These copies are not transformed into subregister insertions/extractions by the PPCVSXCopy class, and so need to be handled directly by PPCInstrInfo::copyPhysReg. The code to do this was *almost* there, but not quite (it was unnecessarily restricting itself to only the direct sub/super-register-class case (not copying between, for example, something in VRRC and the lower-half of VSRC which are super-registers of F8RC). Triggering this behavior manually is difficult; I'm including two bugpoint-reduced test cases from the test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229457 91177308-0d34-0410-b5e6-96231b3b80d8
116 lines
6.4 KiB
LLVM
116 lines
6.4 KiB
LLVM
; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind
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define void @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc(i32* nocapture readonly %first) #0 {
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entry:
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br i1 false, label %loop2_start, label %if.end5
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; CHECK-LABEL: @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc
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; CHECK: xxlor
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loop2_start: ; preds = %loop2_start, %entry
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br i1 undef, label %loop2_start, label %if.then.i31
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if.end5: ; preds = %entry
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br i1 undef, label %loop_start.preheader, label %if.then.i31
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loop_start.preheader: ; preds = %if.end5
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br i1 false, label %middle.block, label %vector.body
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vector.body: ; preds = %vector.body, %loop_start.preheader
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%vec.phi61 = phi <4 x i32> [ %34, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi62 = phi <4 x i32> [ %35, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi63 = phi <4 x i32> [ %36, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi65 = phi <4 x i32> [ %37, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi67 = phi <4 x i32> [ %38, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi68 = phi <4 x i32> [ %39, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi69 = phi <4 x i32> [ %40, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi70 = phi <4 x i32> [ %41, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi71 = phi <4 x i32> [ %42, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%.sum = add i64 0, 4
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%wide.load72 = load <4 x i32>* null, align 4
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%.sum109 = add i64 0, 8
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%0 = getelementptr i32* %first, i64 %.sum109
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%1 = bitcast i32* %0 to <4 x i32>*
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%wide.load73 = load <4 x i32>* %1, align 4
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%.sum110 = add i64 0, 12
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%2 = getelementptr i32* %first, i64 %.sum110
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%3 = bitcast i32* %2 to <4 x i32>*
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%wide.load74 = load <4 x i32>* %3, align 4
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%.sum112 = add i64 0, 20
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%4 = getelementptr i32* %first, i64 %.sum112
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%5 = bitcast i32* %4 to <4 x i32>*
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%wide.load76 = load <4 x i32>* %5, align 4
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%.sum114 = add i64 0, 28
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%6 = getelementptr i32* %first, i64 %.sum114
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%7 = bitcast i32* %6 to <4 x i32>*
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%wide.load78 = load <4 x i32>* %7, align 4
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%.sum115 = add i64 0, 32
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%8 = getelementptr i32* %first, i64 %.sum115
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%9 = bitcast i32* %8 to <4 x i32>*
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%wide.load79 = load <4 x i32>* %9, align 4
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%.sum116 = add i64 0, 36
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%10 = getelementptr i32* %first, i64 %.sum116
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%11 = bitcast i32* %10 to <4 x i32>*
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%wide.load80 = load <4 x i32>* %11, align 4
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%.sum117 = add i64 0, 40
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%12 = getelementptr i32* %first, i64 %.sum117
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%13 = bitcast i32* %12 to <4 x i32>*
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%wide.load81 = load <4 x i32>* %13, align 4
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%.sum118 = add i64 0, 44
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%14 = getelementptr i32* %first, i64 %.sum118
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%15 = bitcast i32* %14 to <4 x i32>*
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%wide.load82 = load <4 x i32>* %15, align 4
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%16 = mul <4 x i32> %wide.load72, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%17 = mul <4 x i32> %wide.load73, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%18 = mul <4 x i32> %wide.load74, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%19 = mul <4 x i32> %wide.load76, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%20 = mul <4 x i32> %wide.load78, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%21 = mul <4 x i32> %wide.load79, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%22 = mul <4 x i32> %wide.load80, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%23 = mul <4 x i32> %wide.load81, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%24 = mul <4 x i32> %wide.load82, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%25 = add <4 x i32> %16, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%26 = add <4 x i32> %17, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%27 = add <4 x i32> %18, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%28 = add <4 x i32> %19, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%29 = add <4 x i32> %20, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%30 = add <4 x i32> %21, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%31 = add <4 x i32> %22, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%32 = add <4 x i32> %23, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%33 = add <4 x i32> %24, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%34 = add nsw <4 x i32> %25, %vec.phi61
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%35 = add nsw <4 x i32> %26, %vec.phi62
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%36 = add nsw <4 x i32> %27, %vec.phi63
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%37 = add nsw <4 x i32> %28, %vec.phi65
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%38 = add nsw <4 x i32> %29, %vec.phi67
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%39 = add nsw <4 x i32> %30, %vec.phi68
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%40 = add nsw <4 x i32> %31, %vec.phi69
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%41 = add nsw <4 x i32> %32, %vec.phi70
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%42 = add nsw <4 x i32> %33, %vec.phi71
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br i1 false, label %middle.block, label %vector.body
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middle.block: ; preds = %vector.body, %loop_start.preheader
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%rdx.vec.exit.phi85 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %34, %vector.body ]
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%rdx.vec.exit.phi86 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %35, %vector.body ]
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%rdx.vec.exit.phi87 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %36, %vector.body ]
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%rdx.vec.exit.phi89 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %37, %vector.body ]
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%rdx.vec.exit.phi91 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %38, %vector.body ]
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%rdx.vec.exit.phi92 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %39, %vector.body ]
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%rdx.vec.exit.phi93 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %40, %vector.body ]
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%rdx.vec.exit.phi94 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %41, %vector.body ]
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%rdx.vec.exit.phi95 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %42, %vector.body ]
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br i1 false, label %if.then.i31, label %loop_start.prol
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loop_start.prol: ; preds = %loop_start.prol, %middle.block
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br label %loop_start.prol
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if.then.i31: ; preds = %middle.block, %if.end5, %loop2_start
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unreachable
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}
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attributes #0 = { nounwind }
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