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7d5a61e975
sure we can emit both the high and low versions of those registers. Fixes rdar://10392864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145579 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
1.0 KiB
LLVM
30 lines
1.0 KiB
LLVM
; RUN: llc < %s -march=x86-64
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; rdar://7066579
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%0 = type { i64, i64, i64, i64, i64 } ; type %0
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define void @test1() nounwind {
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entry:
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%asmtmp = call %0 asm sideeffect "mov %cr0, $0 \0Amov %cr2, $1 \0Amov %cr3, $2 \0Amov %cr4, $3 \0Amov %cr8, $0 \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%0> [#uses=0]
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ret void
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}
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; PR9602
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define void @test2(float %tmp) nounwind {
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call void asm sideeffect "$0", "q"(float %tmp) nounwind
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call void asm sideeffect "$0", "Q"(float %tmp) nounwind
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ret void
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}
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define void @test3(double %tmp) nounwind {
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call void asm sideeffect "$0", "q"(double %tmp) nounwind
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ret void
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}
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; rdar://10392864
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define void @test4(i8 signext %val, i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d) nounwind {
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entry:
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%0 = tail call { i8, i8, i8, i8, i8 } asm "foo $1, $2, $3, $4, $1\0Axchgb ${0:b}, ${0:h}", "=q,={ax},={bx},={cx},={dx},0,1,2,3,4,~{dirflag},~{fpsr},~{flags}"(i8 %val, i8 %a, i8 %b, i8 %c, i8 %d) nounwind
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ret void
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}
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