Daniel Sanders c96096cc0f [mips][mips64r6] Add b[on]vc ... Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209415 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-22 11:23:21 +00:00
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msa	[mips] Move disassembler test (test_2r_msa64) into correct folder.	2014-05-12 16:59:34 +00:00
lit.local.cfg	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
micromips_le.txt	LL and SC decoder method fix.	2014-01-15 13:17:33 +00:00
micromips.txt	LL and SC decoder method fix.	2014-01-15 13:17:33 +00:00
mips32_le.txt	This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.	2014-03-03 13:12:59 +00:00
mips32.txt	This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.	2014-03-03 13:12:59 +00:00
mips32r2_le.txt	This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.	2014-03-03 13:12:59 +00:00
mips32r2.txt	This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.	2014-03-03 13:12:59 +00:00
mips32r6.txt	[mips][mips64r6] Add b[on]vc	2014-05-22 11:23:21 +00:00
mips64_le.txt	[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.	2013-08-28 00:55:15 +00:00
mips64.txt	Mips: Disassemble sign-extended 64 bit immediates properly.	2013-10-11 19:05:08 +00:00
mips64r2_le.txt
mips64r2.txt
mips64r6.txt	[mips][mips64r6] Add b[on]vc	2014-05-22 11:23:21 +00:00
mips-dsp.txt	[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.	2013-08-28 00:55:15 +00:00