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9b22626068
The register spiller assumes that only one new instruction is created when spilling and restoring registers, so we need to emit pseudo instructions for vector register spills and lower them after register allocation. v2: - Fix calculation of lane index - Extend VGPR liveness to end of program. v3: - Use SIMM16 field of S_NOP to specify multiple NOPs. https://bugs.freedesktop.org/show_bug.cgi?id=75005 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207843 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
3.3 KiB
C++
95 lines
3.3 KiB
C++
//===-- SIMachineFunctionInfo.cpp - SI Machine Function Info -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#include "SIMachineFunctionInfo.h"
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#include "SIInstrInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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#define MAX_LANES 64
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using namespace llvm;
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// Pin the vtable to this file.
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void SIMachineFunctionInfo::anchor() {}
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SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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: AMDGPUMachineFunction(MF),
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PSInputAddr(0),
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SpillTracker() { }
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static unsigned createLaneVGPR(MachineRegisterInfo &MRI, MachineFunction *MF) {
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unsigned VGPR = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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// We need to add this register as live out for the function, in order to
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// have the live range calculated directly.
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//
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// When register spilling begins, we have already calculated the live
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// live intervals for all the registers. Since we are spilling SGPRs to
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// VGPRs, we need to update the Lane VGPR's live interval every time we
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// spill or restore a register.
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//
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// Unfortunately, there is no good way to update the live interval as
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// the TargetInstrInfo callbacks for spilling and restoring don't give
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// us access to the live interval information.
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//
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// We are lucky, though, because the InlineSpiller calls
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// LiveRangeEdit::calculateRegClassAndHint() which iterates through
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// all the new register that have been created when restoring a register
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// and calls LiveIntervals::getInterval(), which creates and computes
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// the live interval for the newly created register. However, once this
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// live intervals is created, it doesn't change and since we usually reuse
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// the Lane VGPR multiple times, this means any uses after the first aren't
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// added to the live interval.
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//
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// To work around this, we add Lane VGPRs to the functions live out list,
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// so that we can guarantee its live range will cover all of its uses.
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for (MachineBasicBlock &MBB : *MF) {
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if (MBB.back().getOpcode() == AMDGPU::S_ENDPGM) {
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MBB.back().addOperand(*MF, MachineOperand::CreateReg(VGPR, false, true));
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return VGPR;
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}
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}
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MF->getFunction()->getContext().emitError(
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"Could not found S_ENGPGM instrtuction.");
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return VGPR;
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}
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unsigned SIMachineFunctionInfo::RegSpillTracker::reserveLanes(
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MachineRegisterInfo &MRI, MachineFunction *MF, unsigned NumRegs) {
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unsigned StartLane = CurrentLane;
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CurrentLane += NumRegs;
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if (!LaneVGPR) {
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LaneVGPR = createLaneVGPR(MRI, MF);
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} else {
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if (CurrentLane >= MAX_LANES) {
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StartLane = CurrentLane = 0;
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LaneVGPR = createLaneVGPR(MRI, MF);
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}
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}
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return StartLane;
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}
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void SIMachineFunctionInfo::RegSpillTracker::addSpilledReg(unsigned FrameIndex,
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unsigned Reg,
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int Lane) {
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SpilledRegisters[FrameIndex] = SpilledReg(Reg, Lane);
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}
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const SIMachineFunctionInfo::SpilledReg&
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SIMachineFunctionInfo::RegSpillTracker::getSpilledReg(unsigned FrameIndex) {
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return SpilledRegisters[FrameIndex];
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}
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