llvm-6502/test/CodeGen
Richard Sandiford 8bce43648b [SystemZ] Add support for TMHH, TMHL, TMLH and TMLL
For now this just handles simple comparisons of an ANDed value with zero.
The CC value provides enough information to do any comparison for a
2-bit mask, and some nonzero comparisons with more populated masks,
but that's all future work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189819 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-03 15:38:35 +00:00
..
AArch64
ARM ARM: Default to the Swift CPU when targeting armv7s/thumbv7s. 2013-09-02 17:09:01 +00:00
CPP
Generic
Hexagon
Inputs
Mips Make sure we don't generate stubs for any of these functions because they 2013-09-01 04:12:59 +00:00
MSP430
NVPTX
PowerPC [PowerPC] Call support for fast-isel. 2013-08-30 22:18:55 +00:00
R600 R600/SI: Enable local-memory-two-objects lit test 2013-08-27 10:28:26 +00:00
SPARC [Sparc] Add support for soft long double (fp128). 2013-09-03 04:11:59 +00:00
SystemZ [SystemZ] Add support for TMHH, TMHL, TMLH and TMLL 2013-09-03 15:38:35 +00:00
Thumb ARM: Use "dmb sy" for barriers on M-class CPUs 2013-08-28 14:39:19 +00:00
Thumb2
X86 FileCheck-ize three tests of llvm/test/CodeGen/X86/h-register(s). 2013-09-02 12:00:53 +00:00
XCore