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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144243 91177308-0d34-0410-b5e6-96231b3b80d8
192 lines
6.3 KiB
C++
192 lines
6.3 KiB
C++
//===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the main function for LLVM's TableGen.
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//
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//===----------------------------------------------------------------------===//
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#include "AsmMatcherEmitter.h"
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#include "AsmWriterEmitter.h"
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#include "CallingConvEmitter.h"
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#include "CodeEmitterGen.h"
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#include "DAGISelEmitter.h"
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#include "DisassemblerEmitter.h"
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#include "EDEmitter.h"
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#include "FastISelEmitter.h"
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#include "InstrInfoEmitter.h"
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#include "IntrinsicEmitter.h"
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#include "PseudoLoweringEmitter.h"
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#include "RegisterInfoEmitter.h"
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#include "SubtargetEmitter.h"
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#include "SetTheory.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/PrettyStackTrace.h"
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#include "llvm/Support/Signals.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Main.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenAction.h"
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using namespace llvm;
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enum ActionType {
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PrintRecords,
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GenEmitter,
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GenRegisterInfo,
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GenInstrInfo,
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GenAsmWriter,
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GenAsmMatcher,
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GenDisassembler,
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GenPseudoLowering,
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GenCallingConv,
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GenDAGISel,
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GenFastISel,
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GenSubtarget,
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GenIntrinsic,
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GenTgtIntrinsic,
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GenEDInfo,
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PrintEnums,
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PrintSets
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};
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namespace {
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cl::opt<ActionType>
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Action(cl::desc("Action to perform:"),
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cl::values(clEnumValN(PrintRecords, "print-records",
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"Print all records to stdout (default)"),
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clEnumValN(GenEmitter, "gen-emitter",
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"Generate machine code emitter"),
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clEnumValN(GenRegisterInfo, "gen-register-info",
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"Generate registers and register classes info"),
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clEnumValN(GenInstrInfo, "gen-instr-info",
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"Generate instruction descriptions"),
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clEnumValN(GenCallingConv, "gen-callingconv",
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"Generate calling convention descriptions"),
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clEnumValN(GenAsmWriter, "gen-asm-writer",
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"Generate assembly writer"),
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clEnumValN(GenDisassembler, "gen-disassembler",
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"Generate disassembler"),
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clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
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"Generate pseudo instruction lowering"),
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clEnumValN(GenAsmMatcher, "gen-asm-matcher",
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"Generate assembly instruction matcher"),
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clEnumValN(GenDAGISel, "gen-dag-isel",
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"Generate a DAG instruction selector"),
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clEnumValN(GenFastISel, "gen-fast-isel",
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"Generate a \"fast\" instruction selector"),
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clEnumValN(GenSubtarget, "gen-subtarget",
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"Generate subtarget enumerations"),
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clEnumValN(GenIntrinsic, "gen-intrinsic",
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"Generate intrinsic information"),
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clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic",
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"Generate target intrinsic information"),
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clEnumValN(GenEDInfo, "gen-enhanced-disassembly-info",
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"Generate enhanced disassembly info"),
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clEnumValN(PrintEnums, "print-enums",
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"Print enum values for a class"),
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clEnumValN(PrintSets, "print-sets",
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"Print expanded sets for testing DAG exprs"),
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clEnumValEnd));
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cl::opt<std::string>
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Class("class", cl::desc("Print Enum list for this class"),
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cl::value_desc("class name"));
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}
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class LLVMTableGenAction : public TableGenAction {
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public:
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bool operator()(raw_ostream &OS, RecordKeeper &Records) {
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switch (Action) {
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case PrintRecords:
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OS << Records; // No argument, dump all contents
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break;
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case GenEmitter:
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CodeEmitterGen(Records).run(OS);
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break;
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case GenRegisterInfo:
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RegisterInfoEmitter(Records).run(OS);
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break;
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case GenInstrInfo:
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InstrInfoEmitter(Records).run(OS);
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break;
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case GenCallingConv:
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CallingConvEmitter(Records).run(OS);
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break;
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case GenAsmWriter:
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AsmWriterEmitter(Records).run(OS);
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break;
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case GenAsmMatcher:
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AsmMatcherEmitter(Records).run(OS);
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break;
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case GenDisassembler:
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DisassemblerEmitter(Records).run(OS);
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break;
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case GenPseudoLowering:
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PseudoLoweringEmitter(Records).run(OS);
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break;
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case GenDAGISel:
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DAGISelEmitter(Records).run(OS);
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break;
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case GenFastISel:
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FastISelEmitter(Records).run(OS);
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break;
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case GenSubtarget:
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SubtargetEmitter(Records).run(OS);
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break;
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case GenIntrinsic:
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IntrinsicEmitter(Records).run(OS);
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break;
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case GenTgtIntrinsic:
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IntrinsicEmitter(Records, true).run(OS);
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break;
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case GenEDInfo:
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EDEmitter(Records).run(OS);
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break;
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case PrintEnums:
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{
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std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
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for (unsigned i = 0, e = Recs.size(); i != e; ++i)
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OS << Recs[i]->getName() << ", ";
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OS << "\n";
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break;
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}
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case PrintSets:
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{
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SetTheory Sets;
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Sets.addFieldExpander("Set", "Elements");
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std::vector<Record*> Recs = Records.getAllDerivedDefinitions("Set");
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for (unsigned i = 0, e = Recs.size(); i != e; ++i) {
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OS << Recs[i]->getName() << " = [";
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const std::vector<Record*> *Elts = Sets.expand(Recs[i]);
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assert(Elts && "Couldn't expand Set instance");
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for (unsigned ei = 0, ee = Elts->size(); ei != ee; ++ei)
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OS << ' ' << (*Elts)[ei]->getName();
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OS << " ]\n";
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}
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break;
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}
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default:
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assert(1 && "Invalid Action");
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return true;
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}
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return false;
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}
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};
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int main(int argc, char **argv) {
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sys::PrintStackTraceOnErrorSignal();
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PrettyStackTraceProgram X(argc, argv);
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cl::ParseCommandLineOptions(argc, argv);
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LLVMTableGenAction Action;
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return TableGenMain(argv[0], Action);
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}
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