llvm-6502/test/MC
Bill Schmidt 202b6045bf [PowerPC] Implement the vclz instructions for PWR8
Patch by Kit Barton.

Add the vector count leading zeros instruction for byte, halfword,
word, and doubleword sizes.  This is a fairly straightforward addition
after the changes made for vpopcnt:

 1. Add the correct definitions for the various instructions in
    PPCInstrAltivec.td
 2. Make the CTLZ operation legal on vector types when using P8Altivec
    in PPCISelLowering.cpp 

Test Plan

Created new test case in test/CodeGen/PowerPC/vec_clz.ll to check the
instructions are being generated when the CTLZ operation is used in
LLVM.

Check the encoding and decoding in test/MC/PowerPC/ppc_encoding_vmx.s
and test/Disassembler/PowerPC/ppc_encoding_vmx.txt respectively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228301 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 15:24:47 +00:00
..
AArch64 Fix some unnoticed/unwanted behavior change from r222319. 2015-02-04 03:10:03 +00:00
ARM [ARM] Fix subtarget feature set truncation when using .cpu directive 2015-02-04 16:23:24 +00:00
AsmParser
COFF Bring r226038 back. 2015-01-19 15:16:06 +00:00
Disassembler [PowerPC] Implement the vclz instructions for PWR8 2015-02-05 15:24:47 +00:00
ELF Revert llvm/test/MC/ELF/noexec.s in r227074, "Fix a problem where the AArch64 ELF assembler was failing with" 2015-01-26 09:30:29 +00:00
Hexagon
MachO Add r224985 back with fixes. 2015-01-19 21:11:14 +00:00
Markup
Mips [mips] Manually replace JAL pseudo-instructions with their JALR equivalent, instead of using InstAlias. 2015-01-30 11:18:50 +00:00
PowerPC [PowerPC] Implement the vclz instructions for PWR8 2015-02-05 15:24:47 +00:00
R600
Sparc
SystemZ
X86 [X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output. 2015-02-03 11:03:57 +00:00