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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209456 91177308-0d34-0410-b5e6-96231b3b80d8
110 lines
3.8 KiB
TableGen
110 lines
3.8 KiB
TableGen
//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains DAG node defintions for the AMDGPU target.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// AMDGPU DAG Profiles
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//===----------------------------------------------------------------------===//
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def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
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]>;
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//===----------------------------------------------------------------------===//
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// AMDGPU DAG Nodes
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//
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// This argument to this node is a dword address.
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def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
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// out = a - floor(a)
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def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
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// out = max(a, b) a and b are floats
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def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// out = max(a, b) a and b are signed ints
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def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// out = max(a, b) a and b are unsigned ints
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def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// out = min(a, b) a and b are floats
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def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// out = min(a, b) a snd b are signed ints
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def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// out = min(a, b) a and b are unsigned ints
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def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// urecip - This operation is a helper for integer division, it returns the
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// result of 1 / a as a fractional unsigned integer.
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// out = (2^32 / a) + e
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// e is rounding error
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def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
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def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
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SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
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[SDNPHasChain, SDNPMayLoad]>;
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def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
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SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
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[SDNPHasChain, SDNPMayStore]>;
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// MSKOR instructions are atomic memory instructions used mainly for storing
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// 8-bit and 16-bit values. The definition is:
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//
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// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
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//
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// src0: vec4(src, 0, 0, mask)
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// src1: dst - rat offset (aka pointer) in dwords
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def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
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SDTypeProfile<0, 2, []>,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def AMDGPUround : SDNode<"ISD::FROUND",
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
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def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
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// Signed and unsigned 24-bit mulitply. The highest 8-bits are ignore when
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// performing the mulitply. The result is a 32-bit value.
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def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
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[SDNPCommutative]
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>;
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def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
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[SDNPCommutative]
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>;
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def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
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[]
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>;
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def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
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[]
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>;
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