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llvm-6502/lib/Target/R600
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Matt Arsenault bf933548ba R600/SI: Fix pattern variable names. 
These are confusing enough since the order swaps,
so give them more useful names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209787 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-29 01:18:01 +00:00
..
InstPrinter
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MCTargetDesc
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TargetInfo
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AMDGPU.h
R600: Add definition for flat address space ID.
2014-05-22 18:27:07 +00:00
AMDGPU.td
R600/SI: Add a PredicateControl class for managing TableGen predicates
2014-05-16 20:56:45 +00:00
AMDGPUAsmPrinter.cpp
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AMDGPUAsmPrinter.h
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AMDGPUCallingConv.td
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AMDGPUConvertToISA.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUInstrInfo.cpp
R600/SI: Refactor the VOP3_32 tablegen class
2014-05-16 20:56:47 +00:00
AMDGPUInstrInfo.h
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AMDGPUInstrInfo.td
R600: Add intrinsics for mad24
2014-05-22 18:00:15 +00:00
AMDGPUInstructions.td
R600: Expand mul24 for GPUs without it
2014-05-22 18:00:24 +00:00
AMDGPUIntrinsics.td
R600: Add intrinsics for mad24
2014-05-22 18:00:15 +00:00
AMDGPUISelDAGToDAG.cpp
R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0
2014-05-15 14:41:54 +00:00
AMDGPUISelLowering.cpp
R600: Try to convert BFE back to standard bit ops when possible.
2014-05-22 18:09:12 +00:00
AMDGPUISelLowering.h
R600: Implement ComputeNumSignBitsForTargetNode for BFE
2014-05-22 18:09:03 +00:00
AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPUMCInstLower.cpp
Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended.
2014-05-19 14:29:04 +00:00
AMDGPUMCInstLower.h
R600/SI: Refactor the VOP3_32 tablegen class
2014-05-16 20:56:47 +00:00
AMDGPURegisterInfo.cpp
Use range for
2014-05-15 21:44:05 +00:00
AMDGPURegisterInfo.h
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AMDGPURegisterInfo.td
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AMDGPUSubtarget.cpp
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AMDGPUSubtarget.h
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AMDGPUTargetMachine.cpp
R600: Add definition for flat address space ID.
2014-05-22 18:27:07 +00:00
AMDGPUTargetMachine.h
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AMDGPUTargetTransformInfo.cpp
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AMDILBase.td
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AMDILCFGStructurizer.cpp
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AMDILInstrInfo.td
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AMDILIntrinsicInfo.cpp
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AMDILIntrinsicInfo.h
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AMDILIntrinsics.td
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AMDILISelLowering.cpp
Use range for
2014-05-15 21:44:05 +00:00
AMDILRegisterInfo.td
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CaymanInstructions.td
R600: Expand mul24 for GPUs without it
2014-05-22 18:00:24 +00:00
CMakeLists.txt
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EvergreenInstructions.td
R600: Expand mul24 for GPUs without it
2014-05-22 18:00:24 +00:00
LLVMBuild.txt
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Makefile
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Processors.td
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600InstrFormats.td
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R600InstrInfo.cpp
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R600InstrInfo.h
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R600Instructions.td
R600: Expand mul24 for GPUs without it
2014-05-22 18:00:24 +00:00
R600Intrinsics.td
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R600ISelLowering.cpp
R600: Add dag combine for BFE
2014-05-22 18:09:07 +00:00
R600ISelLowering.h
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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R600MachineScheduler.h
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
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R700Instructions.td
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SIAnnotateControlFlow.cpp
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SIDefines.h
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SIFixSGPRCopies.cpp
R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopies
2014-05-15 14:41:55 +00:00
SIInsertWaits.cpp
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SIInstrFormats.td
R600/SI: Add a PredicateControl class for managing TableGen predicates
2014-05-16 20:56:45 +00:00
SIInstrInfo.cpp
R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopies
2014-05-15 14:41:55 +00:00
SIInstrInfo.h
R600/SI: Refactor the VOP3_32 tablegen class
2014-05-16 20:56:47 +00:00
SIInstrInfo.td
R600/SI: Refactor the VOP3_32 tablegen class
2014-05-16 20:56:47 +00:00
SIInstructions.td
R600/SI: Fix pattern variable names.
2014-05-29 01:18:01 +00:00
SIIntrinsics.td
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SIISelLowering.cpp
R600: Add dag combine for BFE
2014-05-22 18:09:07 +00:00
SIISelLowering.h
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SILowerControlFlow.cpp
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SILowerI1Copies.cpp
R600/SI: Use VALU instructions for i1 ops
2014-05-15 14:41:50 +00:00
SIMachineFunctionInfo.cpp
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SIMachineFunctionInfo.h
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SIRegisterInfo.cpp
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SIRegisterInfo.h
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SIRegisterInfo.td
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SISchedule.td
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SITypeRewriter.cpp
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