Tom Stellard f15dfe4eb4 R600: Set scheduling preference to Sched::Source ... R600 doesn't need to do any scheduling on the SelectionDAG now that it has a very good MachineScheduler. Also, using the VLIW SelectionDAG scheduler was having a major impact on compile times. For example with the phatk kernel here are the LLVM IR to machine code compile times: With Sched::VLIW Total Compile Time: 1.4890 Seconds (User + System) SelectionDAG Instruction Scheduling: 1.1670 Seconds (User + System) With Sched::Source Total Compile Time: 0.3330 Seconds (User + System) SelectionDAG Instruction Scheduling: 0.0070 Seconds (User + System) The code ouput was identical with both schedulers. This may not be true for all programs, but it gives me confidence that there won't be much reduction, if any, in code quality by using Sched::Source. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188215 91177308-0d34-0410-b5e6-96231b3b80d8		2013-08-12 22:33:21 +00:00
..
InstPrinter
MCTargetDesc
TargetInfo
AMDGPU.h	R600/SI: Use VSrc_* register classes as the default classes for types	2013-08-06 23:08:28 +00:00
AMDGPU.td
AMDGPUAsmPrinter.cpp
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td	R600: Add 64-bit float load/store support	2013-08-01 15:23:42 +00:00
AMDGPUConvertToISA.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUIndirectAddressing.cpp
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td
AMDGPUInstructions.td	R600: Add support for 24-bit MUL instructions	2013-07-23 01:48:42 +00:00
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp	R600/SI: Use VSrc_* register classes as the default classes for types	2013-08-06 23:08:28 +00:00
AMDGPUISelLowering.cpp	R600: Implement TargetLowering::getVectorIdxTy()	2013-08-05 22:22:07 +00:00
AMDGPUISelLowering.h	R600: Implement TargetLowering::getVectorIdxTy()	2013-08-05 22:22:07 +00:00
AMDGPUMachineFunction.cpp	Move string pointer from being a static class member to just a static global in the one file its needed in.	2013-07-17 00:31:35 +00:00
AMDGPUMachineFunction.h	Move string pointer from being a static class member to just a static global in the one file its needed in.	2013-07-17 00:31:35 +00:00
AMDGPUMCInstLower.cpp
AMDGPUMCInstLower.h
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp
AMDGPUSubtarget.h
AMDGPUTargetMachine.cpp	R600/SI: Use VSrc_* register classes as the default classes for types	2013-08-06 23:08:28 +00:00
AMDGPUTargetMachine.h	SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions	2013-07-27 00:01:07 +00:00
AMDGPUTargetTransformInfo.cpp	SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions	2013-07-27 00:01:07 +00:00
AMDILBase.td
AMDILCFGStructurizer.cpp	R600: Remove predicated_break inst	2013-07-31 19:31:14 +00:00
AMDILInstrInfo.td
AMDILIntrinsicInfo.cpp
AMDILIntrinsicInfo.h
AMDILIntrinsics.td
AMDILISelLowering.cpp	Make some arrays 'static const'	2013-07-15 06:39:13 +00:00
AMDILRegisterInfo.td
CMakeLists.txt	R600: Add new file from r187831 to CMakeLists.txt	2013-08-06 23:12:34 +00:00
LLVMBuild.txt
Makefile
Processors.td
R600ControlFlowFinalizer.cpp	R600: Add 64-bit float load/store support	2013-08-01 15:23:42 +00:00
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp	R600: Remove predicated_break inst	2013-07-31 19:31:14 +00:00
R600InstrFormats.td	Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"	2013-07-31 20:43:03 +00:00
R600InstrInfo.cpp	R600: Add 64-bit float load/store support	2013-08-01 15:23:42 +00:00
R600InstrInfo.h	Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"	2013-07-31 20:43:03 +00:00
R600Instructions.td	R600: Add 64-bit float load/store support	2013-08-01 15:23:42 +00:00
R600Intrinsics.td
R600ISelLowering.cpp	R600: Set scheduling preference to Sched::Source	2013-08-12 22:33:21 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
R600MachineScheduler.h	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
R600OptimizeVectorRegisters.cpp	R600: Do not mergevector after a vector reg is used	2013-07-31 19:32:12 +00:00
R600Packetizer.cpp	Revert "R600: Non vector only instruction can be scheduled on trans unit"	2013-07-31 20:43:27 +00:00
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td	R600: Add 64-bit float load/store support	2013-08-01 15:23:42 +00:00
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
SIAnnotateControlFlow.cpp	Add 'const' qualifiers to static const char* variables.	2013-07-16 01:17:10 +00:00
SIDefines.h
SIFixSGPRCopies.cpp	R600/SI: Use VSrc_* register classes as the default classes for types	2013-08-06 23:08:28 +00:00
SIInsertWaits.cpp	Initialize SIInsertWaits::ExpInstrTypesSeen in the pass constructor.	2013-08-07 07:47:41 +00:00
SIInstrFormats.td
SIInstrInfo.cpp	Make some arrays 'static const'	2013-07-15 06:39:13 +00:00
SIInstrInfo.h
SIInstrInfo.td	R600/SI: Implement sint<->fp64 conversions	2013-08-08 16:06:08 +00:00
SIInstructions.td	R600/SI: Add FMA pattern	2013-08-10 10:38:47 +00:00
SIIntrinsics.td
SIISelLowering.cpp	R600/SI: FMA is faster than fmul and fadd for f64	2013-08-10 10:38:54 +00:00
SIISelLowering.h	R600/SI: FMA is faster than fmul and fadd for f64	2013-08-10 10:38:54 +00:00
SILowerControlFlow.cpp
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIRegisterInfo.cpp	R600/SI: Add more special cases for opcodes to ensureSRegLimit()	2013-08-06 23:08:18 +00:00
SIRegisterInfo.h	R600/SI: Add more special cases for opcodes to ensureSRegLimit()	2013-08-06 23:08:18 +00:00
SIRegisterInfo.td	R600/SI: Add support for v2f32 loads	2013-07-18 21:43:48 +00:00
SISchedule.td