Misha Brukman dfbfc57d78 Fixed the number translation scheme for the integer condition code registers: it ... now works in instructions which require a 2-bit or 3-bit INTcc code. Incidentally, that means that the representation of INTcc registers is now the same in both integer and FP instructions. Thus, code became much simpler and cleaner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7185 91177308-0d34-0410-b5e6-96231b3b80d8		2003-07-16 20:30:40 +00:00
..
InstrSched
InstrSelection
LiveVar
ModuloScheduling
RegAlloc
.cvsignore
EmitBytecodeToAssembly.cpp
MachineCodeForInstruction.h
MachineFunctionInfo.h
MachineInstrAnnot.h
Makefile
MappingInfo.cpp
MappingInfo.h
SparcV9_F2.td	Encode predict = 1 by default, because the Sparc assembler does this.	2003-07-15 21:26:49 +00:00
SparcV9_F3.td	No need for a second immediate field if the class already inherits one.	2003-07-15 21:27:14 +00:00
SparcV9_F4.td	The name should really be `simm11' to follow the naming convention, but this has	2003-07-16 20:27:44 +00:00
SparcV9_Reg.td
SparcV9.burg.in	Fold cast-to-bool into not. Later, this should also be folded into other	2003-07-10 19:47:42 +00:00
SparcV9.td
SparcV9AsmPrinter.cpp	The word separate' only has one e'.	2003-07-14 17:20:40 +00:00
SparcV9CodeEmitter.cpp	Fixed the number translation scheme for the integer condition code registers: it	2003-07-16 20:30:40 +00:00
SparcV9CodeEmitter.h	Fixed the number translation scheme for the integer condition code registers: it	2003-07-16 20:30:40 +00:00
SparcV9Instr.def
SparcV9InstrInfo.cpp	Bug fix in creating constants: need 1U << 31, not 1 << 31.	2003-07-10 19:48:19 +00:00
SparcV9InstrSelection.cpp	Several important bug fixes:	2003-07-10 20:07:54 +00:00
SparcV9InstrSelectionSupport.h
SparcV9Internals.h
SparcV9PeepholeOpts.cpp
SparcV9PreSelection.cpp
SparcV9PrologEpilogInserter.cpp
SparcV9RegClassInfo.cpp
SparcV9RegClassInfo.h
SparcV9RegInfo.cpp
SparcV9SchedInfo.cpp
SparcV9StackSlots.cpp
SparcV9TargetMachine.cpp