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546952fd60
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78736 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
1.9 KiB
TableGen
50 lines
1.9 KiB
TableGen
//===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Functional units across ARM processors
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//
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def FU_Issue : FuncUnit; // issue
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def FU_Pipe0 : FuncUnit; // pipeline 0
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def FU_Pipe1 : FuncUnit; // pipeline 1
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def FU_LdSt0 : FuncUnit; // pipeline 0 load/store
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def FU_LdSt1 : FuncUnit; // pipeline 1 load/store
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for ARM
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//
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def IIC_iALU : InstrItinClass;
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def IIC_iMPY : InstrItinClass;
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def IIC_iLoad : InstrItinClass;
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def IIC_iStore : InstrItinClass;
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def IIC_fpALU : InstrItinClass;
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def IIC_fpMPY : InstrItinClass;
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def IIC_fpLoad : InstrItinClass;
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def IIC_fpStore : InstrItinClass;
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def IIC_Br : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Processor instruction itineraries.
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def GenericItineraries : ProcessorItineraries<[
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InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMPY , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>
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]>;
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include "ARMScheduleV6.td"
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include "ARMScheduleV7.td"
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