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3c92309f0d
The existing matcher has lots of AT&T assembly dialect assumptions baked into it. In particular, the hack for resolving the size of a memory operand by appending the four most common suffixes doesn't work at all. The Intel assembly dialect mnemonic table has ambiguous entries, so we need to try matching multiple times with different operand sizes, since that's the only way to choose different instruction variants. This makes us more compatible with gas's implementation of Intel assembly syntax. MSVC assumes you want byte-sized operations for the instructions that we reject as ambiguous. Reviewed By: grosbach Differential Revision: http://reviews.llvm.org/D4747 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216481 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| AArch64 | ||
| ARM | ||
| AsmParser | ||
| COFF | ||
| Disassembler | ||
| ELF | ||
| MachO | ||
| Markup | ||
| Mips | ||
| PowerPC | ||
| Sparc | ||
| SystemZ | ||
| X86 | ||