Nick Lewycky c06b5bf340 Add a DAGCombine for (ext (binop (load x), cst)). ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133124 91177308-0d34-0410-b5e6-96231b3b80d8

2011-06-16 01:15:49 +00:00

..

CMakeLists.txt

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DAGCombiner.cpp

Add a DAGCombine for (ext (binop (load x), cst)).

2011-06-16 01:15:49 +00:00

FastISel.cpp

PR10077: fix fast-isel of extractvalue of aggregate constants.

2011-06-06 05:46:34 +00:00

FunctionLoweringInfo.cpp

Add a parameter to CCState so that it can access the MachineFunction.

2011-06-08 23:55:35 +00:00

InstrEmitter.cpp

Use TRI::has{Sub,Super}ClassEq() where possible.

2011-06-02 05:43:46 +00:00

InstrEmitter.h

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LegalizeDAG.cpp

Add a testcase for checking the integer-promotion of many different vector

2011-06-14 08:11:52 +00:00

LegalizeFloatTypes.cpp

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LegalizeIntegerTypes.cpp

getZeroExtendInReg needs to get a scalar type

2011-06-15 14:37:18 +00:00

LegalizeTypes.cpp

Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use

2011-06-01 19:47:10 +00:00

LegalizeTypes.h

Enable the simplification of truncating-store after fixing the usage of

2011-06-15 11:19:12 +00:00

LegalizeTypesGeneric.cpp

Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use

2011-06-01 19:47:10 +00:00

LegalizeVectorOps.cpp

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LegalizeVectorTypes.cpp

Fix a bug in FindMemType. When widening vector loads, use a wider memory type

2011-06-13 18:13:24 +00:00

Makefile

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ScheduleDAGFast.cpp

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ScheduleDAGList.cpp

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ScheduleDAGRRList.cpp

Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.

2011-06-15 23:35:18 +00:00

ScheduleDAGSDNodes.cpp

Added -stress-sched flag in the Asserts build.

2011-06-15 17:16:12 +00:00

ScheduleDAGSDNodes.h

Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.

2011-06-15 23:35:18 +00:00

SDNodeDbgValue.h

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SDNodeOrdering.h

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SelectionDAG.cpp

Remove dead code.

2011-05-24 18:27:52 +00:00

SelectionDAGBuilder.cpp

Add one more argument to the prefetch intrinsic to indicate whether it's a data

2011-06-14 04:58:37 +00:00

SelectionDAGBuilder.h

Preserve debug info during iSel by keeping DanglingDebugInfoMap live until end of function.

2011-05-23 17:44:13 +00:00

SelectionDAGISel.cpp

Remove unused statistical counter.

2011-05-25 21:55:40 +00:00

SelectionDAGPrinter.cpp

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TargetLowering.cpp

Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd

2011-06-12 14:56:55 +00:00

TargetSelectionDAGInfo.cpp

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