Tom Stellard c1de569ce8 R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0 ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208886 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-15 14:41:54 +00:00
..
AArch64	ARM64: print correct aliases for NEON mov & mvn instructions	2014-05-15 12:11:02 +00:00
ARM	Rename ComputeMaskedBits to computeKnownBits. "Masked" has been	2014-05-14 21:14:37 +00:00
ARM64	ARM64: print correct aliases for NEON mov & mvn instructions	2014-05-15 12:11:02 +00:00
CPP
Generic
Hexagon	DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.	2014-05-14 21:52:46 +00:00
Inputs
Mips
MSP430
NVPTX
PowerPC	DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.	2014-05-14 21:52:46 +00:00
R600	R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0	2014-05-15 14:41:54 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	Rename ComputeMaskedBits to computeKnownBits. "Masked" has been	2014-05-14 21:14:37 +00:00
XCore