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https://github.com/c64scene-ar/llvm-6502.git
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7728f7e890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53277 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
3.2 KiB
C++
75 lines
3.2 KiB
C++
//===- Mips.td - Describe the Mips Target Machine ---------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This is the top level entry point for the Mips target.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces
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//===----------------------------------------------------------------------===//
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "MipsRegisterInfo.td"
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include "MipsSchedule.td"
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include "MipsInstrInfo.td"
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include "MipsCallingConv.td"
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def MipsInstrInfo : InstrInfo {
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let TSFlagsFields = [];
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let TSFlagsShifts = [];
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}
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//===----------------------------------------------------------------------===//
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// Mips Subtarget features //
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//===----------------------------------------------------------------------===//
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def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
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"General Purpose Registers are 64-bit wide.">;
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def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
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"Support 64-bit FP registers.">;
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def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
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"true", "Only supports single precision float">;
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def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
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"Mips2 ISA Support">;
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def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
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"Enable o32 ABI">;
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def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
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"Enable eabi ABI">;
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def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
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"true", "Enable vector FPU instructions.">;
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def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
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"Enable 'signext in register' instructions.">;
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//===----------------------------------------------------------------------===//
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// Mips processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, MipsGenericItineraries, Features>;
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def : Proc<"mips1", []>;
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def : Proc<"r2000", []>;
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def : Proc<"r3000", []>;
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def : Proc<"mips2", [FeatureMips2]>;
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def : Proc<"r6000", [FeatureMips2]>;
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// Allegrex is a 32bit subset of r4000, both for interger and fp registers,
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// but much more similar to Mips2 than Mips3.
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def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI,
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FeatureSEInReg, FeatureVFPU]>;
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def Mips : Target {
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let InstructionSet = MipsInstrInfo;
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}
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