Sanjay Patel e53dbeb2ad [X86, AVX] improve insertion into zero element of 256-bit vector ... This patch allows AVX blend instructions to handle insertion into the low element of a 256-bit vector for the appropriate data types. For f32, instead of: vblendps $1, %xmm1, %xmm0, %xmm1 ## xmm1 = xmm1[0],xmm0[1,2,3] vblendps $15, %ymm1, %ymm0, %ymm0 ## ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] we get: vblendps $1, %ymm1, %ymm0, %ymm0 ## ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7] For f64, instead of: vmovsd %xmm1, %xmm0, %xmm1 ## xmm1 = xmm1[0],xmm0[1] vblendpd $3, %ymm1, %ymm0, %ymm0 ## ymm0 = ymm1[0,1],ymm0[2,3] we get: vblendpd $1, %ymm1, %ymm0, %ymm0 ## ymm0 = ymm1[0],ymm0[1,2,3] For the hardware-neglected integer data types, I left a TODO comment in the code and added regression tests for a follow-on patch. Differential Revision: http://reviews.llvm.org/D8609 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233199 91177308-0d34-0410-b5e6-96231b3b80d8		2015-03-25 17:36:01 +00:00
..
AArch64	[AArch64, ARM] Enable GlobalMerge with -O3 rather than -O1.	2015-03-23 21:17:36 +00:00
ARM	[AArch64, ARM] Enable GlobalMerge with -O3 rather than -O1.	2015-03-23 21:17:36 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips	[mips] Support 16-bit offsets for 'm' inline assembly memory constraint.	2015-03-24 15:19:14 +00:00
MSP430
NVPTX
PowerPC	[SDAG] Don't widen VSETCC during type legalization for split operands	2015-03-23 08:22:43 +00:00
R600	R600/SI: Select V_BFE_U32 for and+shift with a non-literal offset	2015-03-24 13:40:34 +00:00
SPARC
SystemZ
Thumb	[ARM] Fix handling of thumb1 out-of-range frame offsets	2015-03-20 17:20:07 +00:00
Thumb2	Fix a nasty bug in DAGCombine of STORE nodes.	2015-03-19 22:48:57 +00:00
WinEH	Fixing a bug with WinEH PHI handling	2015-03-20 21:42:54 +00:00
X86	[X86, AVX] improve insertion into zero element of 256-bit vector	2015-03-25 17:36:01 +00:00
XCore