Jakob Stoklund Olesen 45c5c57179 Allow overlaps between virtreg and physreg live ranges. ... The RegisterCoalescer understands overlapping live ranges where one register is defined as a copy of the other. With this change, register allocators using LiveRegMatrix can do the same, at least for copies between physical and virtual registers. When a physreg is defined by a copy from a virtreg, allow those live ranges to overlap: %CL<def> = COPY %vreg11:sub_8bit; GR32_ABCD:%vreg11 %vreg13<def,tied1> = SAR32rCL %vreg13<tied0>, %CL<imp-use,kill> We can assign %vreg11 to %ECX, overlapping the live range of %CL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163336 91177308-0d34-0410-b5e6-96231b3b80d8		2012-09-06 18:15:23 +00:00
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ARM	Improve codegen for BUILD_VECTORs on ARM.	2012-09-06 09:55:02 +00:00
CellSPU	Add test triples to fix win32 failures. Revert workaround from r161292.	2012-08-08 20:31:37 +00:00
CPP	test commit	2012-07-18 17:53:05 +00:00
Generic	BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle	2012-08-24 18:14:27 +00:00
Hexagon	LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the	2012-09-05 16:01:40 +00:00
MBlaze	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
Mips	Fix UseInitArray option for MIPS target.	2012-09-05 06:17:17 +00:00
MSP430	Reapply r161633-161634 "Partition use lists so defs always come before uses.""	2012-08-10 00:21:30 +00:00
NVPTX	Add llvm.fabs intrinsic.	2012-05-28 21:48:37 +00:00
PowerPC	Allow overlaps between virtreg and physreg live ranges.	2012-09-06 18:15:23 +00:00
SPARC	test/CodeGen/SPARC/private.ll: Fixup. Forgot to prune old RUN lines.	2012-07-03 04:29:20 +00:00
Thumb	Fix Thumb2 fixup kind in the integrated-as.	2012-09-01 15:06:36 +00:00
Thumb2	Use predication instead of pseudo-opcodes when folding into MOVCC.	2012-09-05 23:58:02 +00:00
X86	Allow overlaps between virtreg and physreg live ranges.	2012-09-06 18:15:23 +00:00
XCore	Fix pattern for MKMSK instruction.	2012-06-13 17:59:12 +00:00