llvm-6502/lib/CodeGen/SelectionDAG
Evan Cheng c384d6c398 - Change AssignTopologicalOrder to return vector of SDNode* by reference.
- Tweak implementation to avoid using std::map.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29479 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-02 22:00:34 +00:00
..
DAGCombiner.cpp Initialize some variables the compiler warns about. 2006-07-25 20:44:41 +00:00
LegalizeDAG.cpp Fix a case where LegalizeAllNodesNotLeadingTo could take exponential time. 2006-07-26 23:55:56 +00:00
Makefile For PR780: 2006-07-26 16:18:00 +00:00
ScheduleDAG.cpp Use an enumeration to eliminate data relocations. 2006-07-21 20:57:35 +00:00
ScheduleDAGList.cpp Final polish on machine pass registries. 2006-08-02 12:30:23 +00:00
ScheduleDAGRRList.cpp Final polish on machine pass registries. 2006-08-02 12:30:23 +00:00
ScheduleDAGSimple.cpp Final polish on machine pass registries. 2006-08-02 12:30:23 +00:00
SelectionDAG.cpp - Change AssignTopologicalOrder to return vector of SDNode* by reference. 2006-08-02 22:00:34 +00:00
SelectionDAGISel.cpp Final polish on machine pass registries. 2006-08-02 12:30:23 +00:00
SelectionDAGPrinter.cpp For PR801: 2006-06-27 16:49:46 +00:00
TargetLowering.cpp Fix a typo that causes 2006-07-07-ComputeMaskedBits.ll to fail. 2006-07-07 21:37:21 +00:00