Samuel Antao f75bfbea17 Fix bug in GPR to FPR moves in PPC64LE. ... The current implementation of GPR->FPR register moves uses a stack slot. This mechanism writes a double word and reads a word. In big-endian the load address must be displaced by 4-bytes in order to get the right value. In little endian this is no longer required. This patch fixes the issue and adds LE regression tests to fast-isel-conversion which currently expose this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219441 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-09 20:42:56 +00:00
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AArch64	[AArch64] Generate vector signed/unsigned mul and mla/mls long.	2014-10-08 02:31:24 +00:00
ARM	Emit unaligned access build attribute for ARM	2014-10-08 12:26:22 +00:00
CPP
Generic	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Hexagon	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Inputs	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Mips	[mips] Return {f128} correctly for N32/N64.	2014-10-07 09:29:59 +00:00
MSP430
NVPTX
PowerPC	Fix bug in GPR to FPR moves in PPC64LE.	2014-10-09 20:42:56 +00:00
R600	R600/SI: Legalize CopyToReg during instruction selection	2014-10-09 19:06:00 +00:00
SPARC
SystemZ
Thumb	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Thumb2
X86	[AVX512] Intrinsics for vextract*x4	2014-10-08 23:25:37 +00:00
XCore	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00