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3ddc32292d
On X86, the Intel asm parser tries to match all memory operand sizes when none is explicitly specified. For LEA, which doesn't really have a memory operand (just a pointer one), this results in multiple successful matches, one for each memory size. There's no error because it's same opcode, so really, it's just one match. However, the tablegen'd matcher function adds opcode/operands to the passed MCInst, and this results in multiple duplicated operands. This commit clears the MCInst in the tablegen'd matcher function. We sometimes clear it when the match failed, so there's no expectation of keeping the previous content anyway. Differential Revision: http://reviews.llvm.org/D6670 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224347 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
686 B
ArmAsm
30 lines
686 B
ArmAsm
// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -mcpu=knl %s | FileCheck %s
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// Check that we deduce unsized memory operands in the general, unambiguous, case.
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// We can't deduce xword memory operands, because there is no instruction
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// unambiguously accessing 80-bit memory.
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// CHECK: movb %al, (%rax)
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mov [rax], al
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// CHECK: movw %ax, (%rax)
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mov [rax], ax
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// CHECK: movl %eax, (%rax)
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mov [rax], eax
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// CHECK: movq %rax, (%rax)
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mov [rax], rax
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// CHECK: movdqa %xmm0, (%rax)
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movdqa [rax], xmm0
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// CHECK: vmovdqa %ymm0, (%rax)
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vmovdqa [rax], ymm0
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// CHECK: vaddps (%rax), %zmm1, %zmm1
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vaddps zmm1, zmm1, [rax]
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// CHECK: leal 1(%r15d), %r9d
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lea r9d, [r15d+1]
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