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c3ff3f42ee
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right instructions are still usable as zero and sign extensions. This adds new F3_Sr and F3_Si instruction formats that probably should be used for the 32-bit shifts as well. They don't really encode an simm13 field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178525 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
64bit.ll | ||
2006-01-22-BitConvertLegalize.ll | ||
2007-05-09-JumpTables.ll | ||
2007-07-05-LiveIntervalAssert.ll | ||
2008-10-10-InlineAsmMemoryOperand.ll | ||
2008-10-10-InlineAsmRegOperand.ll | ||
2009-08-28-PIC.ll | ||
2009-08-28-WeakLinkage.ll | ||
2011-01-11-Call.ll | ||
2011-01-11-CC.ll | ||
2011-01-11-FrameAddr.ll | ||
2011-01-19-DelaySlot.ll | ||
2011-01-21-ByValArgs.ll | ||
2011-01-22-SRet.ll | ||
2011-12-03-TailDuplication.ll | ||
2012-05-01-LowerArguments.ll | ||
basictest.ll | ||
ctpop.ll | ||
DbgValueOtherTargets.test | ||
lit.local.cfg | ||
mult-alt-generic-sparc.ll | ||
private.ll |