Hal Finkel c482454e3c Create an new preheader in PPCCTRLoops to avoid counter register clobbers ... Some IR-level instructions (such as FP <-> i64 conversions) are not chained w.r.t. the mtctr intrinsic and yet may become function calls that clobber the counter register. At the selection-DAG level, these might be reordered with the mtctr intrinsic causing miscompiles. To avoid this situation, if an existing preheader has instructions that might use the counter register, create a new preheader for the mtctr intrinsic. This extra block will be remerged with the old preheader at the MI level, but will prevent unwanted reordering at the selection-DAG level. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182045 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-16 19:58:38 +00:00
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Analysis	AArch64: use MCJIT by default and enable related tests.	2013-05-06 16:51:08 +00:00
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BugPoint
CodeGen	Create an new preheader in PPCCTRLoops to avoid counter register clobbers	2013-05-16 19:58:38 +00:00
DebugInfo	Give the test from r181632 a target triple.	2013-05-10 22:14:39 +00:00
ExecutionEngine	XFAIL this test for mingw too.	2013-05-13 00:18:24 +00:00
Feature
FileCheck	Add 'CHECK-DAG' support	2013-05-14 20:34:12 +00:00
Instrumentation	[msan] Switch TLS globals to initial-exec model.	2013-05-16 09:14:05 +00:00
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MC	Mips assembler: Add branch macro definitions	2013-05-16 19:40:19 +00:00
Object	Object: Fix Mach-O relocation printing.	2013-05-14 22:41:29 +00:00
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Transforms	Respect the 'nobuiltin' attribute when determining if a call is to a memory builtin.	2013-05-16 04:12:04 +00:00
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lit.cfg	AArch64: use MCJIT by default and enable related tests.	2013-05-06 16:51:08 +00:00
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