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https://github.com/c64scene-ar/llvm-6502.git
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cdda88cd12
implement a movcond instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29857 91177308-0d34-0410-b5e6-96231b3b80d8
129 lines
4.7 KiB
TableGen
129 lines
4.7 KiB
TableGen
//===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the "Instituto Nokia de Tecnologia" and
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// is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the ARM instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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// Address operands
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def memri : Operand<iPTR> {
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let PrintMethod = "printMemRegImm";
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let NumMIOperands = 2;
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let MIOperandInfo = (ops i32imm, ptr_rc);
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}
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// Define ARM specific addressing mode.
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//register plus/minus 12 bit offset
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def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex]>;
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//register plus scaled register
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//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
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let Namespace = "ARM";
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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def brtarget : Operand<OtherVT>;
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// Operand for printing out a condition code.
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let PrintMethod = "printCCOperand" in
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def CCOp : Operand<i32>;
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def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
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def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
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[SDNPHasChain, SDNPOptInFlag]>;
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def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
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def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
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def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
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def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
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def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
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def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
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"!ADJCALLSTACKUP $amt",
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[(callseq_end imm:$amt)]>;
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def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start imm:$amt)]>;
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let isReturn = 1 in {
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def bx: InstARM<(ops), "bx r14", [(retflag)]>;
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}
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let Defs = [R0, R1, R2, R3, R14] in {
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def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
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}
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def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
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"ldr $dst, $addr",
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[(set IntRegs:$dst, (load iaddr:$addr))]>;
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def str : InstARM<(ops IntRegs:$src, memri:$addr),
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"str $src, $addr",
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[(store IntRegs:$src, iaddr:$addr)]>;
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def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
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"mov $dst, $src", []>;
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def movri : InstARM<(ops IntRegs:$dst, i32imm:$src),
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"mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;
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def addri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
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"add $dst, $a, $b",
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[(set IntRegs:$dst, (add IntRegs:$a, imm:$b))]>;
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// "LEA" forms of add
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def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
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"add $dst, ${addr:arith}",
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[(set IntRegs:$dst, iaddr:$addr)]>;
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def subri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
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"sub $dst, $a, $b",
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[(set IntRegs:$dst, (sub IntRegs:$a, imm:$b))]>;
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def andrr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
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"and $dst, $a, $b",
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[(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
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let isTwoAddress = 1 in {
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def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true, CCOp:$cc),
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"mov$cc $dst, $true",
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[(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false, imm:$cc))]>;
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}
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def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
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"b$cc $dst",
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[(armbr bb:$dst, imm:$cc)]>;
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def cmp : InstARM<(ops IntRegs:$a, IntRegs:$b),
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"cmp $a, $b",
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[(armcmp IntRegs:$a, IntRegs:$b)]>;
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