Ahmed Bougacha c52cd839b9 [AArch64] Improve codegen of store lane 0 instructions by directly storing the subregister. ... For 0-lane stores, we used to generate code similar to: fmov w8, s0 str w8, [x0, x1, lsl #2] instead of: str s0, [x0, x1, lsl #2] To correct that: for store lane 0 patterns, directly match to STR <subreg>0. Byte-sized instructions don't have the special case for a 0 index, because FPR8s are defined to have untyped content. rdar://16372710 Differential Revision: http://reviews.llvm.org/D6772 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225181 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-05 17:02:28 +00:00
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AArch64	[AArch64] Improve codegen of store lane 0 instructions by directly storing the subregister.	2015-01-05 17:02:28 +00:00
ARM	Emit the build attribute Tag_conformance.	2015-01-05 13:12:17 +00:00
CPP
Generic	CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.	2014-12-19 20:50:07 +00:00
Hexagon	[Hexagon] Adding reg-reg indexed load forms.	2014-12-30 18:58:47 +00:00
Inputs	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Mips	[mips][microMIPS] Fix bugs related to atomic SC/LL instructions	2014-12-18 16:39:29 +00:00
MSP430
NVPTX	[NVPTX] Fix bugs related to isSingleValueType	2014-12-17 17:59:04 +00:00
PowerPC	[PowerPC] Enable speculation of cttz/ctlz	2015-01-05 05:24:42 +00:00
R600	Enable (sext x) == C --> x == (trunc C) combine	2014-12-21 16:48:42 +00:00
SPARC	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
SystemZ	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Thumb	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Thumb2	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
X86	[X86][SSE] Added vector packing test for pr12412	2015-01-04 19:08:03 +00:00
XCore	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00