Bill Schmidt c5ca284e85 Merging r214716: ...

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r214716 | uweigand | 2014-08-04 08:27:12 -0500 (Mon, 04 Aug 2014) | 9 lines

[PowerPC] MULHU/MULHS are not legal for vector types

I ran into some test failures where common code changed vector division
by constant into a multiply-high operation (MULHU).  But these are not
implemented by the back-end, so we failed to recognize the insn.

Fixed by marking MULHU/MULHS as Expand for vector types.


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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@214818 91177308-0d34-0410-b5e6-96231b3b80d8

2014-08-04 23:41:27 +00:00

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AArch64

CodeGen: emit IR-level f16 conversion intrinsics as fptrunc/fpext

2014-07-21 09:13:56 +00:00

ARM

Replace the result usages while legalizing cmpxchg.

2014-07-21 17:33:44 +00:00

CPP

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Generic

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Hexagon

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Inputs

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Mips

Merging r214180:

2014-07-30 12:39:37 +00:00

MSP430

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NVPTX

Merging r213773:

2014-07-30 14:49:09 +00:00

PowerPC

Merging r214716:

2014-08-04 23:41:27 +00:00

R600

R600/SI: Add instruction shrinking pass

2014-07-21 16:55:33 +00:00

SPARC

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SystemZ

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Thumb

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Thumb2

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X86

Merging r213798:

2014-07-31 18:17:04 +00:00

XCore

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