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f4e104f5eb
Since the result of a SETCC for AArch64 is 0 or -1 in each lane, we can
move unary operations, in this case [su]int_to_fp through the mask
operation and constant fold the operation away. Generally speaking:
UNARYOP(AND(VECTOR_CMP(x,y), constant))
--> AND(VECTOR_CMP(x,y), constant2)
where constant2 is UNARYOP(constant).
This implements the transform where UNARYOP is [su]int_to_fp.
For example, consider the simple function:
define <4 x float> @foo(<4 x float> %val, <4 x float> %test) nounwind {
%cmp = fcmp oeq <4 x float> %val, %test
%ext = zext <4 x i1> %cmp to <4 x i32>
%result = sitofp <4 x i32> %ext to <4 x float>
ret <4 x float> %result
}
Before this change, the code is generated as:
fcmeq.4s v0, v0, v1
movi.4s v1, #0x1 // Integer splat value.
and.16b v0, v0, v1 // Mask lanes based on the comparison.
scvtf.4s v0, v0 // Convert each lane to f32.
ret
After, the code is improved to:
fcmeq.4s v0, v0, v1
fmov.4s v1, #1.00000000 // f32 splat value.
and.16b v0, v0, v1 // Mask lanes based on the comparison.
ret
The svvtf.4s has been constant folded away and the floating point 1.0f
vector lanes are materialized directly via fmov.4s.
Rather than do the folding manually in the target code, teach getNode()
in the generic SelectionDAG to handle folding constant operands of
vector [su]int_to_fp nodes. It is reasonable (as noted in a FIXME) to do
additional constant folding there as well, but I don't have test cases
for those operations, so leaving them for another time when it becomes
appropriate.
rdar://17693791
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213341 91177308-0d34-0410-b5e6-96231b3b80d8
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| .. | ||
| AsmParser | ||
| Disassembler | ||
| InstPrinter | ||
| MCTargetDesc | ||
| TargetInfo | ||
| Utils | ||
| AArch64.h | ||
| AArch64.td | ||
| AArch64AddressTypePromotion.cpp | ||
| AArch64AdvSIMDScalarPass.cpp | ||
| AArch64AsmPrinter.cpp | ||
| AArch64BranchRelaxation.cpp | ||
| AArch64CallingConvention.td | ||
| AArch64CleanupLocalDynamicTLSPass.cpp | ||
| AArch64CollectLOH.cpp | ||
| AArch64ConditionalCompares.cpp | ||
| AArch64DeadRegisterDefinitionsPass.cpp | ||
| AArch64ExpandPseudoInsts.cpp | ||
| AArch64FastISel.cpp | ||
| AArch64FrameLowering.cpp | ||
| AArch64FrameLowering.h | ||
| AArch64InstrAtomics.td | ||
| AArch64InstrFormats.td | ||
| AArch64InstrInfo.cpp | ||
| AArch64InstrInfo.h | ||
| AArch64InstrInfo.td | ||
| AArch64ISelDAGToDAG.cpp | ||
| AArch64ISelLowering.cpp | ||
| AArch64ISelLowering.h | ||
| AArch64LoadStoreOptimizer.cpp | ||
| AArch64MachineFunctionInfo.h | ||
| AArch64MCInstLower.cpp | ||
| AArch64MCInstLower.h | ||
| AArch64PerfectShuffle.h | ||
| AArch64PromoteConstant.cpp | ||
| AArch64RegisterInfo.cpp | ||
| AArch64RegisterInfo.h | ||
| AArch64RegisterInfo.td | ||
| AArch64SchedA53.td | ||
| AArch64SchedA57.td | ||
| AArch64SchedA57WriteRes.td | ||
| AArch64SchedCyclone.td | ||
| AArch64Schedule.td | ||
| AArch64SelectionDAGInfo.cpp | ||
| AArch64SelectionDAGInfo.h | ||
| AArch64StorePairSuppress.cpp | ||
| AArch64Subtarget.cpp | ||
| AArch64Subtarget.h | ||
| AArch64TargetMachine.cpp | ||
| AArch64TargetMachine.h | ||
| AArch64TargetObjectFile.cpp | ||
| AArch64TargetObjectFile.h | ||
| AArch64TargetTransformInfo.cpp | ||
| CMakeLists.txt | ||
| LLVMBuild.txt | ||
| Makefile | ||