llvm-6502/lib/CodeGen
2010-12-22 22:01:28 +00:00
..
AsmPrinter Add missing standard headers. Patch by Joerg Sonnenberger! 2010-12-19 20:43:38 +00:00
SelectionDAG Fix a bug in ReduceLoadWidth that wasn't handling extending 2010-12-22 08:02:57 +00:00
AggressiveAntiDepBreaker.cpp Simplify AggressiveAntiDepBreaker's use of register aliases. 2010-12-14 23:23:15 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp Use AllocationOrder in RegAllocGreedy, fix a bug in the hint calculation. 2010-12-10 22:21:05 +00:00
AllocationOrder.h Add an AllocationOrder class that can iterate over the allocatable physical 2010-12-10 18:36:02 +00:00
Analysis.cpp Enable sibling call optimization of libcalls which are expanded during 2010-11-30 23:55:39 +00:00
AntiDepBreaker.h
BranchFolding.cpp
BranchFolding.h
CalcSpillWeights.cpp
CallingConvLower.cpp Simplify CCState's use of register aliases. 2010-12-14 23:28:01 +00:00
CMakeLists.txt Add MachineLoopRanges analysis. 2010-12-15 23:41:23 +00:00
CodeGen.cpp Stub out a new LiveDebugVariables pass. 2010-11-30 02:17:10 +00:00
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp
DwarfEHPrepare.cpp
ELF.h Merge System into Support. 2010-11-29 18:16:10 +00:00
ELFCodeEmitter.cpp
ELFCodeEmitter.h
ELFWriter.cpp Fixed version of 121434 with no new memory leaks. 2010-12-10 07:39:47 +00:00
ELFWriter.h
ExpandISelPseudos.cpp Rename ExpandPseudos to ExpandISelPseudos to help clarify its role. 2010-11-18 18:45:06 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp Move some more hooks to TargetFrameInfo 2010-11-20 15:59:32 +00:00
IfConversion.cpp Prune includes. 2010-11-06 11:45:59 +00:00
InlineSpiller.cpp Apparently, operandices is not a word. 2010-12-18 03:28:32 +00:00
IntrinsicLowering.cpp
LatencyPriorityQueue.cpp
LiveDebugVariables.cpp Rename virtRegMap to avoid confusion with the VirtRegMap that it isn't. 2010-12-03 22:25:09 +00:00
LiveDebugVariables.h Emit DBG_VALUE instructions from LiveDebugVariables. 2010-12-03 21:47:10 +00:00
LiveInterval.cpp Use IntEqClasses to compute connected components of live intervals. 2010-12-21 00:48:17 +00:00
LiveIntervalAnalysis.cpp Fix emergency spilling in LiveIntervals::spillPhysRegAroundRegDefsUses. 2010-11-16 19:55:14 +00:00
LiveIntervalUnion.cpp Avoid dereferencing end() in collectInterferingVRegs() when there is no 2010-12-17 23:16:38 +00:00
LiveIntervalUnion.h Provide LiveIntervalUnion::Query::checkLoopInterference. 2010-12-17 04:09:47 +00:00
LiveRangeEdit.cpp Simplify the LiveRangeEdit::canRematerializeAt() interface a bit. 2010-11-10 01:05:12 +00:00
LiveRangeEdit.h Teach the inline spiller to attempt folding a load instruction into its single 2010-12-18 03:04:14 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp
LLVMTargetMachine.cpp Pass a Banner argument to the machine code verifier both from 2010-12-18 00:06:56 +00:00
LocalStackSlotAllocation.cpp During local stack slot allocation, the materializeFrameBaseRegister function 2010-12-17 23:09:14 +00:00
LowerSubregs.cpp
MachineBasicBlock.cpp
MachineCSE.cpp Teach machine cse to commute instructions. 2010-12-15 22:16:21 +00:00
MachineDominators.cpp
MachineFunction.cpp move the pic base symbol stuff up to MachineFunction 2010-11-14 22:48:15 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp
MachineLICM.cpp Add a FIXME comment. 2010-11-11 18:08:43 +00:00
MachineLoopInfo.cpp
MachineLoopRanges.cpp Add MachineLoopRange comparators for sorting loop lists by number and by area. 2010-12-17 18:13:52 +00:00
MachineModuleInfo.cpp Fixed version of 121434 with no new memory leaks. 2010-12-10 07:39:47 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp
MachineSink.cpp
MachineSSAUpdater.cpp
MachineVerifier.cpp MachineVerifier should count landing pad successors as basic blocks rather than 2010-12-20 04:19:48 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp
PeepholeOptimizer.cpp Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, 2010-11-17 20:13:28 +00:00
PHIElimination.cpp Remove the PHIElimination.h header, as it is no longer needed. 2010-12-05 21:39:42 +00:00
PHIEliminationUtils.cpp Move the FindCopyInsertPoint method of PHIElimination to a new standalone 2010-12-05 19:51:05 +00:00
PHIEliminationUtils.h Move the FindCopyInsertPoint method of PHIElimination to a new standalone 2010-12-05 19:51:05 +00:00
PostRASchedulerList.cpp
PreAllocSplitting.cpp Remove some checks for StrongPHIElim. These checks make it impossible to use an 2010-12-19 18:03:27 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp Move more PEI-related hooks to TFI 2010-11-27 23:05:25 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp Merge System into Support. 2010-11-29 18:16:10 +00:00
README.txt
RegAllocBase.h Make the -verify-regalloc command line option available to base classes as 2010-12-17 23:16:35 +00:00
RegAllocBasic.cpp Pass a Banner argument to the machine code verifier both from 2010-12-18 00:06:56 +00:00
RegAllocFast.cpp Fix comment. 2010-12-08 21:35:09 +00:00
RegAllocGreedy.cpp Tweak debug spew. 2010-12-18 03:04:11 +00:00
RegAllocLinearScan.cpp Emit DBG_VALUE instructions from LiveDebugVariables. 2010-12-03 21:47:10 +00:00
RegAllocPBQP.cpp Fix some style issues in PBQP. Patch by David Blaikie. 2010-11-12 05:47:21 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp
RenderMachineFunction.cpp
RenderMachineFunction.h
ScheduleDAG.cpp reduce indentation, no functionality change. 2010-12-20 00:50:16 +00:00
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp Move Value::getUnderlyingObject to be a standalone 2010-12-15 20:02:24 +00:00
ScheduleDAGInstrs.h
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp Generalize PostRAHazardRecognizer so it can be used in any pass for 2010-12-08 20:04:29 +00:00
ShadowStackGC.cpp
ShrinkWrapping.cpp
SimpleRegisterCoalescing.cpp Remove some checks for StrongPHIElim. These checks make it impossible to use an 2010-12-19 18:03:27 +00:00
SimpleRegisterCoalescing.h Implement the first half of LiveDebugVariables. 2010-12-02 00:37:37 +00:00
SjLjEHPrepare.cpp Prune includes. 2010-11-06 11:45:59 +00:00
SlotIndexes.cpp Insert two blank SlotIndexes between basic blocks instead of just one. 2010-11-11 00:19:20 +00:00
Spiller.cpp Force the greedy register allocator to always use the inline spiller. 2010-12-10 22:54:44 +00:00
Spiller.h Force the greedy register allocator to always use the inline spiller. 2010-12-10 22:54:44 +00:00
SplitKit.cpp Include a shadow of the original CFG edges in the edge bundle graph. 2010-12-22 22:01:28 +00:00
SplitKit.h Add EdgeBundles to SplitKit. 2010-12-21 01:50:21 +00:00
Splitter.cpp
Splitter.h
StackProtector.cpp
StackSlotColoring.cpp
StrongPHIElimination.cpp Incremental progress towards a new implementation of StrongPHIElimination. Most 2010-12-21 06:54:43 +00:00
TailDuplication.cpp
TargetInstrInfoImpl.cpp Generalize PostRAHazardRecognizer so it can be used in any pass for 2010-12-08 20:04:29 +00:00
TargetLoweringObjectFileImpl.cpp Fixed version of 121434 with no new memory leaks. 2010-12-10 07:39:47 +00:00
TwoAddressInstructionPass.cpp StrongPHIElimination will never run before TwoAddressInstructionPass. 2010-12-19 21:32:29 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Remember to resize SpillSlotToUsesMap when allocating an emergency spill slot. 2010-11-16 00:41:01 +00:00
VirtRegMap.h Add an AllocationOrder class that can iterate over the allocatable physical 2010-12-10 18:36:02 +00:00
VirtRegRewriter.cpp Prune includes. 2010-11-06 11:45:59 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.