llvm-6502/lib/Target/Sparc
Daniel Dunbar e28039cfd1 Move most targets TargetMachine constructor to only taking a target triple.
- The C, C++, MSIL, and Mips backends still need the module.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77927 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-02 23:37:13 +00:00
..
AsmPrinter pass the mangler down into the various SectionForGlobal methods. 2009-07-29 05:09:30 +00:00
TargetInfo Normalize target registration code. 2009-07-31 18:16:53 +00:00
CMakeLists.txt CMake build fixes, from Xerxes Ranby 2009-07-02 18:53:52 +00:00
DelaySlotFiller.cpp
FPMover.cpp llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 2009-07-14 16:55:14 +00:00
Makefile Add TargetInfo libraries for all targets. 2009-07-15 06:35:19 +00:00
README.txt
Sparc.h Add new helpers for registering targets. 2009-07-25 06:49:55 +00:00
Sparc.td
SparcCallingConv.td
SparcInstrFormats.td
SparcInstrInfo.cpp Remove unused member functions. 2009-07-24 07:43:59 +00:00
SparcInstrInfo.h Remove unused member functions. 2009-07-24 07:43:59 +00:00
SparcInstrInfo.td
SparcISelDAGToDAG.cpp Implement changes from Chris's feedback. 2009-07-08 20:53:28 +00:00
SparcISelLowering.cpp Rip all of the global variable lowering logic out of TargetAsmInfo. Since 2009-07-28 03:13:23 +00:00
SparcISelLowering.h Don't override LowerArguments in the SPARC backend. In addition to 2009-07-19 19:53:46 +00:00
SparcRegisterInfo.cpp llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 2009-07-14 16:55:14 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSubtarget.cpp Normalize Subtarget constructors to take a target triple string instead of 2009-08-02 22:11:08 +00:00
SparcSubtarget.h Normalize Subtarget constructors to take a target triple string instead of 2009-08-02 22:11:08 +00:00
SparcTargetAsmInfo.cpp eliminate TargetMAchine argument to sparc TAI 2009-08-02 04:30:59 +00:00
SparcTargetAsmInfo.h eliminate TargetMAchine argument to sparc TAI 2009-08-02 04:30:59 +00:00
SparcTargetMachine.cpp Move most targets TargetMachine constructor to only taking a target triple. 2009-08-02 23:37:13 +00:00
SparcTargetMachine.h Move most targets TargetMachine constructor to only taking a target triple. 2009-08-02 23:37:13 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots