llvm-6502/test/CodeGen/Thumb/barrier.ll
Evan Cheng c7569ed4e4 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit
instructions: dmb, dsb, isb, msr, and mrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:30:38 +00:00

25 lines
578 B
LLVM

; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s -check-prefix=V6
; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=M0
declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1 )
define void @t1() {
; V6: t1:
; V6: blx {{_*}}sync_synchronize
; M0: t1:
; M0: dsb
call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 true )
ret void
}
define void @t2() {
; V6: t2:
; V6: blx {{_*}}sync_synchronize
; M0: t2:
; M0: dmb
call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 false )
ret void
}