Evan Cheng c7569ed4e4 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit ... instructions: dmb, dsb, isb, msr, and mrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8		2010-08-11 06:30:38 +00:00
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Alpha	PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually	2010-08-01 21:13:28 +00:00
ARM	Update test to match output of optimize compares for ARM.	2010-08-11 01:05:02 +00:00
Blackfin
CBackend
CellSPU	Have SPU handle halfvec stores aligned by 8 bytes.	2010-08-09 16:33:00 +00:00
CPP
Generic	Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself	2010-07-27 18:02:18 +00:00
MBlaze
Mips	Fix PR7174, a couple o Mips fixes:	2010-07-20 08:37:04 +00:00
MSP430
PIC16
PowerPC	PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.	2010-08-02 00:18:19 +00:00
SPARC
SystemZ
Thumb	Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit	2010-08-11 06:30:38 +00:00
Thumb2	- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the	2010-08-11 06:22:01 +00:00
X86	Fix test for more architectures. Patch by Tobias Grosser.	2010-08-10 16:48:24 +00:00
XCore