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c781a243a3
VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants. Not yet enabled. This is part 1. More coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70787 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.8 KiB
C++
58 lines
1.8 KiB
C++
//===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the live stack slot analysis pass. It is analogous to
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// live interval analysis except it's analyzing liveness of stack slots rather
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// than registers.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "livestacks"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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char LiveStacks::ID = 0;
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static RegisterPass<LiveStacks> X("livestacks", "Live Stack Slot Analysis");
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void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void LiveStacks::releaseMemory() {
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// Release VNInfo memroy regions after all VNInfo objects are dtor'd.
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VNInfoAllocator.Reset();
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S2IMap.clear();
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S2RCMap.clear();
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}
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bool LiveStacks::runOnMachineFunction(MachineFunction &) {
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// FIXME: No analysis is being done right now. We are relying on the
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// register allocators to provide the information.
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return false;
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}
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/// print - Implement the dump method.
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void LiveStacks::print(std::ostream &O, const Module*) const {
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O << "********** INTERVALS **********\n";
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for (const_iterator I = begin(), E = end(); I != E; ++I) {
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I->second.print(O);
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int Slot = I->first;
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const TargetRegisterClass *RC = getIntervalRegClass(Slot);
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if (RC)
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O << " [" << RC->getName() << "]\n";
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else
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O << " [Unknown]\n";
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}
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}
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