llvm-6502/lib/CodeGen
Evan Cheng c781a243a3 In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all.
VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.

Not yet enabled. This is part 1. More coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70787 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-03 18:32:42 +00:00
..
AsmPrinter -Move the DwarfWriter::ValidDebugInfo check to a static DIDescriptor::ValidDebugInfo 2009-05-03 08:50:41 +00:00
SelectionDAG Fix typo 2009-05-03 13:19:57 +00:00
BranchFolding.cpp
CMakeLists.txt update 2009-03-11 22:52:25 +00:00
DeadMachineInstructionElim.cpp
ELFWriter.cpp Introduce new linkage types linkonce_odr, weak_odr, common_odr 2009-03-07 15:45:40 +00:00
ELFWriter.h
GCMetadata.cpp Eliminate several more unnecessary intptr_t casts. 2009-02-18 05:09:16 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp Eliminate several more unnecessary intptr_t casts. 2009-02-18 05:09:16 +00:00
IfConversion.cpp
IntrinsicLowering.cpp Introduce new linkage types linkonce_odr, weak_odr, common_odr 2009-03-07 15:45:40 +00:00
LatencyPriorityQueue.cpp
LiveInterval.cpp Fix PR4034. Bug in LiveInterval::join when it's compacting new valno's. 2009-04-28 06:24:09 +00:00
LiveIntervalAnalysis.cpp In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. 2009-05-03 18:32:42 +00:00
LiveStackAnalysis.cpp In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. 2009-05-03 18:32:42 +00:00
LiveVariables.cpp
LLVMTargetMachine.cpp Instead of passing in an unsigned value for the optimization level, use an enum, 2009-04-29 23:29:43 +00:00
LoopAligner.cpp
LowerSubregs.cpp Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86 2009-03-23 07:19:58 +00:00
MachineBasicBlock.cpp Reapply 68073, with fixes. EH Landing-pad basic blocks are not 2009-03-31 18:39:13 +00:00
MachineDominators.cpp Eliminate several more unnecessary intptr_t casts. 2009-02-18 05:09:16 +00:00
MachineFunction.cpp Make DebugLoc independent of DwarfWriter. 2009-04-30 23:22:31 +00:00
MachineInstr.cpp Make DebugLoc independent of DwarfWriter. 2009-04-30 23:22:31 +00:00
MachineLICM.cpp MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. 2009-02-27 00:02:22 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp DebugLabelFolder ruthlessly deletes redundant labels. However, sometimes the redundant labels is referenced by debug info somewhere else. This patch provies a way so that dwarf writer can mark labels as used. 2009-04-10 18:58:59 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Move MachineRegisterInfo::setRegClass out of line. 2009-04-15 01:19:35 +00:00
MachineSink.cpp fix two problems with machine sinking: 2009-04-10 16:38:36 +00:00
MachOWriter.cpp It makes no sense to have a ODR version of common 2009-03-11 20:14:15 +00:00
MachOWriter.h
Makefile
OcamlGC.cpp
Passes.cpp
PBQP.cpp
PBQP.h
PHIElimination.cpp Reapply r67049, with the test adjusted for darwin 2009-03-17 09:46:22 +00:00
PostRASchedulerList.cpp Fix pr3954. The register scavenger asserts for inline assembly with 2009-04-09 17:16:43 +00:00
PreAllocSplitting.cpp In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. 2009-05-03 18:32:42 +00:00
PrologEpilogInserter.cpp Shrink wrapping in PEI: initial release. Finishing development, enable with --shrink-wrap. 2009-03-27 06:09:40 +00:00
PseudoSourceValue.cpp Now that errs() is properly non-buffered, there's no need to 2009-03-23 15:57:19 +00:00
README.txt
RegAllocBigBlock.cpp
RegAllocLinearScan.cpp In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. 2009-05-03 18:32:42 +00:00
RegAllocLocal.cpp Fix pr3954. The register scavenger asserts for inline assembly with 2009-04-09 17:16:43 +00:00
RegAllocPBQP.cpp In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. 2009-05-03 18:32:42 +00:00
RegAllocSimple.cpp Fix pr3954. The register scavenger asserts for inline assembly with 2009-04-09 17:16:43 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp Fix pr3954. The register scavenger asserts for inline assembly with 2009-04-09 17:16:43 +00:00
ScheduleDAG.cpp
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp
ScheduleDAGInstrs.h
ScheduleDAGPrinter.cpp
ShadowStackGC.cpp Introduce new linkage types linkonce_odr, weak_odr, common_odr 2009-03-07 15:45:40 +00:00
SimpleRegisterCoalescing.cpp Join cross class copies using getCommonSubClass() 2009-04-30 21:24:03 +00:00
SimpleRegisterCoalescing.h Add a smarter heuristic to determine when to coalesce a virtual register with a physical one. More specifically, it avoid tying a virtual register in the loop with a physical register defined / used outside the loop. When it determines it's not profitable, it will use the physical register as the allocation preference instead. 2009-04-30 18:39:57 +00:00
Spiller.cpp It has finally happened. Spiller is now using live interval info. 2009-04-21 22:46:52 +00:00
Spiller.h It has finally happened. Spiller is now using live interval info. 2009-04-21 22:46:52 +00:00
StackProtector.cpp When we split a basic block, there's a default branch to the newly created BB. 2009-03-06 01:41:15 +00:00
StackSlotColoring.cpp In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. 2009-05-03 18:32:42 +00:00
StrongPHIElimination.cpp
TargetInstrInfoImpl.cpp
TwoAddressInstructionPass.cpp Fix for PR4051. When 2address pass delete an instruction, update kill info when necessary. 2009-04-28 02:12:36 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. 2009-05-03 18:32:42 +00:00
VirtRegMap.h In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. 2009-05-03 18:32:42 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4