Chris Lattner c98279d371 Do not codegen 'xor bool, true' as 'not reg'. not reg inverts the upper bits ... of the bytereg. This fixes yacr2, 300.twolf and probably others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19622 91177308-0d34-0410-b5e6-96231b3b80d8		2005-01-17 00:23:16 +00:00
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CBackend	Fix CBE code so that it compiles with VC++.	2005-01-06 04:21:49 +00:00
PowerPC	Fix Regression/CodeGen/PowerPC/2005-01-14-UndefLong.ll	2005-01-14 20:22:02 +00:00
Skeleton	ignore generated files	2004-11-21 00:01:54 +00:00
Sparc	Substantially improve the code generated by non-folded setcc instructions.	2005-01-01 16:06:57 +00:00
SparcV8	Substantially improve the code generated by non-folded setcc instructions.	2005-01-01 16:06:57 +00:00
SparcV9	Added paramters to a few functions in order to allow me to change the functions to preserve SSA	2005-01-16 08:51:10 +00:00
X86	Do not codegen 'xor bool, true' as 'not reg'. not reg inverts the upper bits	2005-01-17 00:23:16 +00:00
Makefile	Add SparcV8 target back into the build	2004-12-10 04:54:21 +00:00
MRegisterInfo.cpp	Move destructor out of line to avoid vtable emission in every file that includes the header. Thanks to sabre.	2004-10-27 06:00:53 +00:00
Target.td	Add some bits that can be set for instructions.	2005-01-02 02:27:48 +00:00
TargetData.cpp	Initial support for packed types, contributed by Morten Ofstad	2004-12-01 17:14:28 +00:00
TargetFrameInfo.cpp	Remove dead methods	2004-08-12 18:37:15 +00:00
TargetInstrInfo.cpp	ConstantTypeMustBeLoaded has been incorporated into SparcV9PreSelection, its	2004-07-27 21:43:38 +00:00
TargetMachine.cpp	Add a new target-independent code generator flag.	2005-01-15 06:00:32 +00:00
TargetMachineRegistry.cpp	Implement TargetRegistrationListener	2004-07-11 06:03:21 +00:00
TargetSchedInfo.cpp	Improve compatiblity with HPUX on Itanium, patch by Duraid Madina	2005-01-16 01:31:31 +00:00