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https://github.com/c64scene-ar/llvm-6502.git
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eedff3547d
- When extloading from a vector with non-byte-addressable element, e.g. <4 x i1>, the current logic breaks. Extend the current logic to fix the case where the element type is not byte-addressable by loading all bytes, bit-extracting/packing each element. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175642 91177308-0d34-0410-b5e6-96231b3b80d8
67 lines
1.2 KiB
LLVM
67 lines
1.2 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s
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define <4 x i3> @test1(<4 x i3>* %in) nounwind {
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%ret = load <4 x i3>* %in, align 1
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ret <4 x i3> %ret
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}
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; CHECK: test1
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; CHECK: movzwl
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; CHECK: shrl $3
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; CHECK: andl $7
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; CHECK: andl $7
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; CHECK: vmovd
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; CHECK: pinsrd $1
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; CHECK: shrl $6
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; CHECK: andl $7
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; CHECK: pinsrd $2
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; CHECK: shrl $9
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; CHECK: andl $7
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; CHECK: pinsrd $3
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; CHECK: ret
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define <4 x i1> @test2(<4 x i1>* %in) nounwind {
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%ret = load <4 x i1>* %in, align 1
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ret <4 x i1> %ret
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}
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; CHECK: test2
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; CHECK: movzbl
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; CHECK: shrl
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; CHECK: andl $1
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; CHECK: andl $1
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; CHECK: vmovd
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; CHECK: pinsrd $1
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; CHECK: shrl $2
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; CHECK: andl $1
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; CHECK: pinsrd $2
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; CHECK: shrl $3
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; CHECK: andl $1
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; CHECK: pinsrd $3
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; CHECK: ret
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define <4 x i64> @test3(<4 x i1>* %in) nounwind {
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%wide.load35 = load <4 x i1>* %in, align 1
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%sext = sext <4 x i1> %wide.load35 to <4 x i64>
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ret <4 x i64> %sext
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}
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; CHECK: test3
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; CHECK: movzbl
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; CHECK: shrl
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; CHECK: andl $1
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; CHECK: andl $1
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; CHECK: vmovd
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; CHECK: pinsrd $1
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; CHECK: shrl $2
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; CHECK: andl $1
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; CHECK: pinsrd $2
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; CHECK: shrl $3
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; CHECK: andl $1
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; CHECK: pinsrd $3
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; CHECK: pslld
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; CHECK: psrad
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; CHECK: pmovsxdq
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; CHECK: pmovsxdq
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; CHECK: ret
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