Cameron Zwarich ca3f6a3925 Add missing register forms of instructions to the ARM CMP-folding code. This ... fixes <rdar://problem/9287901>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129599 91177308-0d34-0410-b5e6-96231b3b80d8		2011-04-15 20:28:28 +00:00
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Alpha	If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.	2010-12-06 22:39:26 +00:00
ARM	Add missing register forms of instructions to the ARM CMP-folding code. This	2011-04-15 20:28:28 +00:00
Blackfin	Don't completely eliminate identity copies that also modify super register liveness.	2011-03-31 17:55:25 +00:00
CBackend
CellSPU	don't test for codegen of 'store undef'	2011-04-09 02:31:26 +00:00
CPP
Generic	Fix a bug where RecursivelyDeleteTriviallyDeadInstructions could	2011-04-09 07:05:44 +00:00
MBlaze	Add scheduling information for the MBlaze backend.	2011-04-11 22:31:52 +00:00
Mips	Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.	2011-04-15 19:52:08 +00:00
MSP430	Enhance ComputeMaskedBits to know that aligned frameindexes	2011-02-13 22:25:43 +00:00
PowerPC	These tests no longer require linear scan because reserved register coalescing is now universal.	2011-04-05 21:40:41 +00:00
PTX	ptx: support setp's 4-operand format	2011-04-02 08:51:39 +00:00
SPARC	These tests no longer require linear scan because reserved register coalescing is now universal.	2011-04-05 21:40:41 +00:00
SystemZ	Fix SystemZ tests	2011-03-31 23:02:12 +00:00
Thumb	Follow up on r127913. Fix Thumb revsh isel. rdar://9286766	2011-04-14 23:27:44 +00:00
Thumb2	Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.	2011-04-13 00:38:32 +00:00
X86	Add 129518 back with a fix for when we are producing eh just because of debug info.	2011-04-15 15:11:06 +00:00
XCore	Fix Mips, Sparc, and XCore tests that were dependent on register allocation.	2011-03-31 18:42:43 +00:00