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Also constrain the register class for branches. This fixes rdar://problem/18181496. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216804 91177308-0d34-0410-b5e6-96231b3b80d8
3484 lines
119 KiB
C++
3484 lines
119 KiB
C++
//===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the AArch64-specific support for the FastISel class. Some
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// of the target-specific code is generated by tablegen in the file
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// AArch64GenFastISel.inc, which is #included here.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64Subtarget.h"
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#include "AArch64TargetMachine.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "llvm/Analysis/BranchProbabilityInfo.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GetElementPtrTypeIterator.h"
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#include "llvm/IR/GlobalAlias.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/Operator.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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namespace {
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class AArch64FastISel : public FastISel {
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class Address {
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public:
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typedef enum {
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RegBase,
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FrameIndexBase
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} BaseKind;
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private:
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BaseKind Kind;
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AArch64_AM::ShiftExtendType ExtType;
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union {
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unsigned Reg;
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int FI;
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} Base;
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unsigned OffsetReg;
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unsigned Shift;
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int64_t Offset;
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const GlobalValue *GV;
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public:
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Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend),
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OffsetReg(0), Shift(0), Offset(0), GV(nullptr) { Base.Reg = 0; }
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void setKind(BaseKind K) { Kind = K; }
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BaseKind getKind() const { return Kind; }
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void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; }
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AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; }
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bool isRegBase() const { return Kind == RegBase; }
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bool isFIBase() const { return Kind == FrameIndexBase; }
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void setReg(unsigned Reg) {
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assert(isRegBase() && "Invalid base register access!");
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Base.Reg = Reg;
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}
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unsigned getReg() const {
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assert(isRegBase() && "Invalid base register access!");
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return Base.Reg;
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}
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void setOffsetReg(unsigned Reg) {
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assert(isRegBase() && "Invalid offset register access!");
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OffsetReg = Reg;
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}
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unsigned getOffsetReg() const {
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assert(isRegBase() && "Invalid offset register access!");
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return OffsetReg;
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}
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void setFI(unsigned FI) {
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assert(isFIBase() && "Invalid base frame index access!");
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Base.FI = FI;
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}
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unsigned getFI() const {
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assert(isFIBase() && "Invalid base frame index access!");
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return Base.FI;
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}
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void setOffset(int64_t O) { Offset = O; }
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int64_t getOffset() { return Offset; }
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void setShift(unsigned S) { Shift = S; }
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unsigned getShift() { return Shift; }
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void setGlobalValue(const GlobalValue *G) { GV = G; }
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const GlobalValue *getGlobalValue() { return GV; }
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};
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/// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const AArch64Subtarget *Subtarget;
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LLVMContext *Context;
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bool FastLowerArguments() override;
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bool FastLowerCall(CallLoweringInfo &CLI) override;
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bool FastLowerIntrinsicCall(const IntrinsicInst *II) override;
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private:
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// Selection routines.
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bool SelectLoad(const Instruction *I);
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bool SelectStore(const Instruction *I);
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bool SelectBranch(const Instruction *I);
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bool SelectIndirectBr(const Instruction *I);
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bool SelectCmp(const Instruction *I);
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bool SelectSelect(const Instruction *I);
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bool SelectFPExt(const Instruction *I);
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bool SelectFPTrunc(const Instruction *I);
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bool SelectFPToInt(const Instruction *I, bool Signed);
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bool SelectIntToFP(const Instruction *I, bool Signed);
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bool SelectRem(const Instruction *I, unsigned ISDOpcode);
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bool SelectRet(const Instruction *I);
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bool SelectTrunc(const Instruction *I);
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bool SelectIntExt(const Instruction *I);
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bool SelectMul(const Instruction *I);
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bool SelectShift(const Instruction *I);
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bool SelectBitCast(const Instruction *I);
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// Utility helper routines.
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
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bool isValueAvailable(const Value *V) const;
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bool ComputeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
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bool ComputeCallAddress(const Value *V, Address &Addr);
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bool SimplifyAddress(Address &Addr, MVT VT);
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void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
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unsigned Flags, unsigned ScaleFactor,
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MachineMemOperand *MMO);
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bool IsMemCpySmall(uint64_t Len, unsigned Alignment);
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bool TryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
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unsigned Alignment);
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bool foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I,
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const Value *Cond);
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// Emit helper routines.
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unsigned emitAddsSubs(bool UseAdds, MVT RetVT, const Value *LHS,
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const Value *RHS, bool IsZExt = false,
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bool WantResult = true);
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unsigned emitAddsSubs_rr(bool UseAdds, MVT RetVT, unsigned LHSReg,
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bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
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bool WantResult = true);
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unsigned emitAddsSubs_ri(bool UseAdds, MVT RetVT, unsigned LHSReg,
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bool LHSIsKill, uint64_t Imm,
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bool WantResult = true);
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unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
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bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
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AArch64_AM::ShiftExtendType ShiftType,
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uint64_t ShiftImm, bool WantResult = true);
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unsigned emitAddsSubs_rs(bool UseAdds, MVT RetVT, unsigned LHSReg,
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bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
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AArch64_AM::ShiftExtendType ShiftType,
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uint64_t ShiftImm, bool WantResult = true);
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unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
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bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
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AArch64_AM::ShiftExtendType ExtType,
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uint64_t ShiftImm, bool WantResult = true);
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unsigned emitAddsSubs_rx(bool UseAdds, MVT RetVT, unsigned LHSReg,
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bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
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AArch64_AM::ShiftExtendType ExtType,
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uint64_t ShiftImm, bool WantResult = true);
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// Emit functions.
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bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
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bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
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bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
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bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
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bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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MachineMemOperand *MMO = nullptr);
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bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
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MachineMemOperand *MMO = nullptr);
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unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
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unsigned Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
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unsigned emitAdds(MVT RetVT, const Value *LHS, const Value *RHS,
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bool IsZExt = false, bool WantResult = true);
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unsigned emitSubs(MVT RetVT, const Value *LHS, const Value *RHS,
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bool IsZExt = false, bool WantResult = true);
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unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
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unsigned RHSReg, bool RHSIsKill, bool WantResult = true);
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unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
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unsigned RHSReg, bool RHSIsKill,
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AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
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bool WantResult = true);
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unsigned emitAND_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
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unsigned Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill);
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unsigned Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill);
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unsigned Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill);
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unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
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unsigned Op1Reg, bool Op1IsKill);
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unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
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uint64_t Imm, bool IsZExt = true);
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unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
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unsigned Op1Reg, bool Op1IsKill);
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unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
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uint64_t Imm, bool IsZExt = true);
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unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
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unsigned Op1Reg, bool Op1IsKill);
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unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
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uint64_t Imm, bool IsZExt = false);
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unsigned AArch64MaterializeInt(const ConstantInt *CI, MVT VT);
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unsigned AArch64MaterializeFP(const ConstantFP *CFP, MVT VT);
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unsigned AArch64MaterializeGV(const GlobalValue *GV);
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// Call handling routines.
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private:
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CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
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bool ProcessCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
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unsigned &NumBytes);
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bool FinishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
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public:
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// Backend specific FastISel code.
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unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
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unsigned TargetMaterializeConstant(const Constant *C) override;
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unsigned TargetMaterializeFloatZero(const ConstantFP* CF) override;
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explicit AArch64FastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo)
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: FastISel(funcInfo, libInfo) {
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Subtarget = &TM.getSubtarget<AArch64Subtarget>();
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Context = &funcInfo.Fn->getContext();
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}
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bool TargetSelectInstruction(const Instruction *I) override;
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#include "AArch64GenFastISel.inc"
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};
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} // end anonymous namespace
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#include "AArch64GenCallingConv.inc"
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CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
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if (CC == CallingConv::WebKit_JS)
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return CC_AArch64_WebKit_JS;
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return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
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}
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unsigned AArch64FastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
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assert(TLI.getValueType(AI->getType(), true) == MVT::i64 &&
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"Alloca should always return a pointer.");
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// Don't handle dynamic allocas.
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if (!FuncInfo.StaticAllocaMap.count(AI))
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return 0;
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DenseMap<const AllocaInst *, int>::iterator SI =
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FuncInfo.StaticAllocaMap.find(AI);
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if (SI != FuncInfo.StaticAllocaMap.end()) {
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unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
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ResultReg)
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.addFrameIndex(SI->second)
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.addImm(0)
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.addImm(0);
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return ResultReg;
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}
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return 0;
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}
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unsigned AArch64FastISel::AArch64MaterializeInt(const ConstantInt *CI, MVT VT) {
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if (VT > MVT::i64)
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return 0;
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if (!CI->isZero())
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return FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
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// Create a copy from the zero register to materialize a "0" value.
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const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
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: &AArch64::GPR32RegClass;
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unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
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unsigned ResultReg = createResultReg(RC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(ZeroReg, getKillRegState(true));
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return ResultReg;
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}
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unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) {
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// Positive zero (+0.0) has to be materialized with a fmov from the zero
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// register, because the immediate version of fmov cannot encode zero.
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if (CFP->isNullValue())
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return TargetMaterializeFloatZero(CFP);
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if (VT != MVT::f32 && VT != MVT::f64)
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return 0;
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const APFloat Val = CFP->getValueAPF();
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bool Is64Bit = (VT == MVT::f64);
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// This checks to see if we can use FMOV instructions to materialize
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// a constant, otherwise we have to materialize via the constant pool.
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if (TLI.isFPImmLegal(Val, VT)) {
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int Imm =
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Is64Bit ? AArch64_AM::getFP64Imm(Val) : AArch64_AM::getFP32Imm(Val);
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assert((Imm != -1) && "Cannot encode floating-point constant.");
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unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi;
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return FastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
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}
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// Materialize via constant pool. MachineConstantPool wants an explicit
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// alignment.
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unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
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if (Align == 0)
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Align = DL.getTypeAllocSize(CFP->getType());
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unsigned CPI = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
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unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
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ADRPReg).addConstantPoolIndex(CPI, 0, AArch64II::MO_PAGE);
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unsigned Opc = Is64Bit ? AArch64::LDRDui : AArch64::LDRSui;
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
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.addReg(ADRPReg)
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.addConstantPoolIndex(CPI, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
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return ResultReg;
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}
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unsigned AArch64FastISel::AArch64MaterializeGV(const GlobalValue *GV) {
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// We can't handle thread-local variables quickly yet.
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if (GV->isThreadLocal())
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return 0;
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// MachO still uses GOT for large code-model accesses, but ELF requires
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// movz/movk sequences, which FastISel doesn't handle yet.
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if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
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return 0;
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unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
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EVT DestEVT = TLI.getValueType(GV->getType(), true);
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if (!DestEVT.isSimple())
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return 0;
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unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
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unsigned ResultReg;
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if (OpFlags & AArch64II::MO_GOT) {
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// ADRP + LDRX
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
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ADRPReg)
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.addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE);
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ResultReg = createResultReg(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
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ResultReg)
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.addReg(ADRPReg)
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.addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
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AArch64II::MO_NC);
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} else {
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// ADRP + ADDX
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
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ADRPReg)
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.addGlobalAddress(GV, 0, AArch64II::MO_PAGE);
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ResultReg = createResultReg(&AArch64::GPR64spRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
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ResultReg)
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.addReg(ADRPReg)
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.addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
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.addImm(0);
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}
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return ResultReg;
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}
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unsigned AArch64FastISel::TargetMaterializeConstant(const Constant *C) {
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EVT CEVT = TLI.getValueType(C->getType(), true);
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// Only handle simple types.
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if (!CEVT.isSimple())
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return 0;
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MVT VT = CEVT.getSimpleVT();
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if (const auto *CI = dyn_cast<ConstantInt>(C))
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return AArch64MaterializeInt(CI, VT);
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else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
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return AArch64MaterializeFP(CFP, VT);
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else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
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return AArch64MaterializeGV(GV);
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return 0;
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}
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unsigned AArch64FastISel::TargetMaterializeFloatZero(const ConstantFP* CFP) {
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assert(CFP->isNullValue() &&
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"Floating-point constant is not a positive zero.");
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MVT VT;
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if (!isTypeLegal(CFP->getType(), VT))
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return 0;
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if (VT != MVT::f32 && VT != MVT::f64)
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return 0;
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bool Is64Bit = (VT == MVT::f64);
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unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
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unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr;
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return FastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true);
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}
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// Computes the address to get to an object.
|
|
bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr, Type *Ty)
|
|
{
|
|
const User *U = nullptr;
|
|
unsigned Opcode = Instruction::UserOp1;
|
|
if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
|
|
// Don't walk into other basic blocks unless the object is an alloca from
|
|
// another block, otherwise it may not have a virtual register assigned.
|
|
if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
|
|
FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
|
|
Opcode = I->getOpcode();
|
|
U = I;
|
|
}
|
|
} else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
|
|
Opcode = C->getOpcode();
|
|
U = C;
|
|
}
|
|
|
|
if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
|
|
if (Ty->getAddressSpace() > 255)
|
|
// Fast instruction selection doesn't support the special
|
|
// address spaces.
|
|
return false;
|
|
|
|
switch (Opcode) {
|
|
default:
|
|
break;
|
|
case Instruction::BitCast: {
|
|
// Look through bitcasts.
|
|
return ComputeAddress(U->getOperand(0), Addr, Ty);
|
|
}
|
|
case Instruction::IntToPtr: {
|
|
// Look past no-op inttoptrs.
|
|
if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
|
|
return ComputeAddress(U->getOperand(0), Addr, Ty);
|
|
break;
|
|
}
|
|
case Instruction::PtrToInt: {
|
|
// Look past no-op ptrtoints.
|
|
if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
|
|
return ComputeAddress(U->getOperand(0), Addr, Ty);
|
|
break;
|
|
}
|
|
case Instruction::GetElementPtr: {
|
|
Address SavedAddr = Addr;
|
|
uint64_t TmpOffset = Addr.getOffset();
|
|
|
|
// Iterate through the GEP folding the constants into offsets where
|
|
// we can.
|
|
gep_type_iterator GTI = gep_type_begin(U);
|
|
for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
|
|
++i, ++GTI) {
|
|
const Value *Op = *i;
|
|
if (StructType *STy = dyn_cast<StructType>(*GTI)) {
|
|
const StructLayout *SL = DL.getStructLayout(STy);
|
|
unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
|
|
TmpOffset += SL->getElementOffset(Idx);
|
|
} else {
|
|
uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
|
|
for (;;) {
|
|
if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
|
|
// Constant-offset addressing.
|
|
TmpOffset += CI->getSExtValue() * S;
|
|
break;
|
|
}
|
|
if (canFoldAddIntoGEP(U, Op)) {
|
|
// A compatible add with a constant operand. Fold the constant.
|
|
ConstantInt *CI =
|
|
cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
|
|
TmpOffset += CI->getSExtValue() * S;
|
|
// Iterate on the other operand.
|
|
Op = cast<AddOperator>(Op)->getOperand(0);
|
|
continue;
|
|
}
|
|
// Unsupported
|
|
goto unsupported_gep;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Try to grab the base operand now.
|
|
Addr.setOffset(TmpOffset);
|
|
if (ComputeAddress(U->getOperand(0), Addr, Ty))
|
|
return true;
|
|
|
|
// We failed, restore everything and try the other options.
|
|
Addr = SavedAddr;
|
|
|
|
unsupported_gep:
|
|
break;
|
|
}
|
|
case Instruction::Alloca: {
|
|
const AllocaInst *AI = cast<AllocaInst>(Obj);
|
|
DenseMap<const AllocaInst *, int>::iterator SI =
|
|
FuncInfo.StaticAllocaMap.find(AI);
|
|
if (SI != FuncInfo.StaticAllocaMap.end()) {
|
|
Addr.setKind(Address::FrameIndexBase);
|
|
Addr.setFI(SI->second);
|
|
return true;
|
|
}
|
|
break;
|
|
}
|
|
case Instruction::Add: {
|
|
// Adds of constants are common and easy enough.
|
|
const Value *LHS = U->getOperand(0);
|
|
const Value *RHS = U->getOperand(1);
|
|
|
|
if (isa<ConstantInt>(LHS))
|
|
std::swap(LHS, RHS);
|
|
|
|
if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
|
|
Addr.setOffset(Addr.getOffset() + (uint64_t)CI->getSExtValue());
|
|
return ComputeAddress(LHS, Addr, Ty);
|
|
}
|
|
|
|
Address Backup = Addr;
|
|
if (ComputeAddress(LHS, Addr, Ty) && ComputeAddress(RHS, Addr, Ty))
|
|
return true;
|
|
Addr = Backup;
|
|
|
|
break;
|
|
}
|
|
case Instruction::Shl:
|
|
if (Addr.getOffsetReg())
|
|
break;
|
|
|
|
if (const auto *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
|
|
unsigned Val = CI->getZExtValue();
|
|
if (Val < 1 || Val > 3)
|
|
break;
|
|
|
|
uint64_t NumBytes = 0;
|
|
if (Ty && Ty->isSized()) {
|
|
uint64_t NumBits = DL.getTypeSizeInBits(Ty);
|
|
NumBytes = NumBits / 8;
|
|
if (!isPowerOf2_64(NumBits))
|
|
NumBytes = 0;
|
|
}
|
|
|
|
if (NumBytes != (1ULL << Val))
|
|
break;
|
|
|
|
Addr.setShift(Val);
|
|
Addr.setExtendType(AArch64_AM::LSL);
|
|
|
|
if (const auto *I = dyn_cast<Instruction>(U->getOperand(0)))
|
|
if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
|
|
U = I;
|
|
|
|
if (const auto *ZE = dyn_cast<ZExtInst>(U))
|
|
if (ZE->getOperand(0)->getType()->isIntegerTy(32))
|
|
Addr.setExtendType(AArch64_AM::UXTW);
|
|
|
|
if (const auto *SE = dyn_cast<SExtInst>(U))
|
|
if (SE->getOperand(0)->getType()->isIntegerTy(32))
|
|
Addr.setExtendType(AArch64_AM::SXTW);
|
|
|
|
unsigned Reg = getRegForValue(U->getOperand(0));
|
|
if (!Reg)
|
|
return false;
|
|
Addr.setOffsetReg(Reg);
|
|
return true;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (Addr.getReg()) {
|
|
if (!Addr.getOffsetReg()) {
|
|
unsigned Reg = getRegForValue(Obj);
|
|
if (!Reg)
|
|
return false;
|
|
Addr.setOffsetReg(Reg);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
unsigned Reg = getRegForValue(Obj);
|
|
if (!Reg)
|
|
return false;
|
|
Addr.setReg(Reg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::ComputeCallAddress(const Value *V, Address &Addr) {
|
|
const User *U = nullptr;
|
|
unsigned Opcode = Instruction::UserOp1;
|
|
bool InMBB = true;
|
|
|
|
if (const auto *I = dyn_cast<Instruction>(V)) {
|
|
Opcode = I->getOpcode();
|
|
U = I;
|
|
InMBB = I->getParent() == FuncInfo.MBB->getBasicBlock();
|
|
} else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
|
|
Opcode = C->getOpcode();
|
|
U = C;
|
|
}
|
|
|
|
switch (Opcode) {
|
|
default: break;
|
|
case Instruction::BitCast:
|
|
// Look past bitcasts if its operand is in the same BB.
|
|
if (InMBB)
|
|
return ComputeCallAddress(U->getOperand(0), Addr);
|
|
break;
|
|
case Instruction::IntToPtr:
|
|
// Look past no-op inttoptrs if its operand is in the same BB.
|
|
if (InMBB &&
|
|
TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
|
|
return ComputeCallAddress(U->getOperand(0), Addr);
|
|
break;
|
|
case Instruction::PtrToInt:
|
|
// Look past no-op ptrtoints if its operand is in the same BB.
|
|
if (InMBB &&
|
|
TLI.getValueType(U->getType()) == TLI.getPointerTy())
|
|
return ComputeCallAddress(U->getOperand(0), Addr);
|
|
break;
|
|
}
|
|
|
|
if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
|
|
Addr.setGlobalValue(GV);
|
|
return true;
|
|
}
|
|
|
|
// If all else fails, try to materialize the value in a register.
|
|
if (!Addr.getGlobalValue()) {
|
|
Addr.setReg(getRegForValue(V));
|
|
return Addr.getReg() != 0;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
|
|
bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
|
|
EVT evt = TLI.getValueType(Ty, true);
|
|
|
|
// Only handle simple types.
|
|
if (evt == MVT::Other || !evt.isSimple())
|
|
return false;
|
|
VT = evt.getSimpleVT();
|
|
|
|
// This is a legal type, but it's not something we handle in fast-isel.
|
|
if (VT == MVT::f128)
|
|
return false;
|
|
|
|
// Handle all other legal types, i.e. a register that will directly hold this
|
|
// value.
|
|
return TLI.isTypeLegal(VT);
|
|
}
|
|
|
|
bool AArch64FastISel::isLoadStoreTypeLegal(Type *Ty, MVT &VT) {
|
|
if (isTypeLegal(Ty, VT))
|
|
return true;
|
|
|
|
// If this is a type than can be sign or zero-extended to a basic operation
|
|
// go ahead and accept it now. For stores, this reflects truncation.
|
|
if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
bool AArch64FastISel::isValueAvailable(const Value *V) const {
|
|
if (!isa<Instruction>(V))
|
|
return true;
|
|
|
|
const auto *I = cast<Instruction>(V);
|
|
if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT) {
|
|
unsigned ScaleFactor;
|
|
switch (VT.SimpleTy) {
|
|
default: return false;
|
|
case MVT::i1: // fall-through
|
|
case MVT::i8: ScaleFactor = 1; break;
|
|
case MVT::i16: ScaleFactor = 2; break;
|
|
case MVT::i32: // fall-through
|
|
case MVT::f32: ScaleFactor = 4; break;
|
|
case MVT::i64: // fall-through
|
|
case MVT::f64: ScaleFactor = 8; break;
|
|
}
|
|
|
|
bool ImmediateOffsetNeedsLowering = false;
|
|
bool RegisterOffsetNeedsLowering = false;
|
|
int64_t Offset = Addr.getOffset();
|
|
if (((Offset < 0) || (Offset & (ScaleFactor - 1))) && !isInt<9>(Offset))
|
|
ImmediateOffsetNeedsLowering = true;
|
|
else if (Offset > 0 && !(Offset & (ScaleFactor - 1)) &&
|
|
!isUInt<12>(Offset / ScaleFactor))
|
|
ImmediateOffsetNeedsLowering = true;
|
|
|
|
// Cannot encode an offset register and an immediate offset in the same
|
|
// instruction. Fold the immediate offset into the load/store instruction and
|
|
// emit an additonal add to take care of the offset register.
|
|
if (!ImmediateOffsetNeedsLowering && Addr.getOffset() && Addr.isRegBase() &&
|
|
Addr.getOffsetReg())
|
|
RegisterOffsetNeedsLowering = true;
|
|
|
|
// Cannot encode zero register as base.
|
|
if (Addr.isRegBase() && Addr.getOffsetReg() && !Addr.getReg())
|
|
RegisterOffsetNeedsLowering = true;
|
|
|
|
// If this is a stack pointer and the offset needs to be simplified then put
|
|
// the alloca address into a register, set the base type back to register and
|
|
// continue. This should almost never happen.
|
|
if (ImmediateOffsetNeedsLowering && Addr.isFIBase()) {
|
|
unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
|
|
ResultReg)
|
|
.addFrameIndex(Addr.getFI())
|
|
.addImm(0)
|
|
.addImm(0);
|
|
Addr.setKind(Address::RegBase);
|
|
Addr.setReg(ResultReg);
|
|
}
|
|
|
|
if (RegisterOffsetNeedsLowering) {
|
|
unsigned ResultReg = 0;
|
|
if (Addr.getReg()) {
|
|
if (Addr.getExtendType() == AArch64_AM::SXTW ||
|
|
Addr.getExtendType() == AArch64_AM::UXTW )
|
|
ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
|
|
/*TODO:IsKill=*/false, Addr.getOffsetReg(),
|
|
/*TODO:IsKill=*/false, Addr.getExtendType(),
|
|
Addr.getShift());
|
|
else
|
|
ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
|
|
/*TODO:IsKill=*/false, Addr.getOffsetReg(),
|
|
/*TODO:IsKill=*/false, AArch64_AM::LSL,
|
|
Addr.getShift());
|
|
} else {
|
|
if (Addr.getExtendType() == AArch64_AM::UXTW)
|
|
ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
|
|
/*Op0IsKill=*/false, Addr.getShift(),
|
|
/*IsZExt=*/true);
|
|
else if (Addr.getExtendType() == AArch64_AM::SXTW)
|
|
ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
|
|
/*Op0IsKill=*/false, Addr.getShift(),
|
|
/*IsZExt=*/false);
|
|
else
|
|
ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(),
|
|
/*Op0IsKill=*/false, Addr.getShift());
|
|
}
|
|
if (!ResultReg)
|
|
return false;
|
|
|
|
Addr.setReg(ResultReg);
|
|
Addr.setOffsetReg(0);
|
|
Addr.setShift(0);
|
|
Addr.setExtendType(AArch64_AM::InvalidShiftExtend);
|
|
}
|
|
|
|
// Since the offset is too large for the load/store instruction get the
|
|
// reg+offset into a register.
|
|
if (ImmediateOffsetNeedsLowering) {
|
|
unsigned ResultReg = 0;
|
|
if (Addr.getReg())
|
|
ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(),
|
|
/*IsKill=*/false, Offset, MVT::i64);
|
|
else
|
|
ResultReg = FastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
|
|
|
|
if (!ResultReg)
|
|
return false;
|
|
Addr.setReg(ResultReg);
|
|
Addr.setOffset(0);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
|
|
const MachineInstrBuilder &MIB,
|
|
unsigned Flags,
|
|
unsigned ScaleFactor,
|
|
MachineMemOperand *MMO) {
|
|
int64_t Offset = Addr.getOffset() / ScaleFactor;
|
|
// Frame base works a bit differently. Handle it separately.
|
|
if (Addr.isFIBase()) {
|
|
int FI = Addr.getFI();
|
|
// FIXME: We shouldn't be using getObjectSize/getObjectAlignment. The size
|
|
// and alignment should be based on the VT.
|
|
MMO = FuncInfo.MF->getMachineMemOperand(
|
|
MachinePointerInfo::getFixedStack(FI, Offset), Flags,
|
|
MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
|
|
// Now add the rest of the operands.
|
|
MIB.addFrameIndex(FI).addImm(Offset);
|
|
} else {
|
|
assert(Addr.isRegBase() && "Unexpected address kind.");
|
|
const MCInstrDesc &II = MIB->getDesc();
|
|
unsigned Idx = (Flags & MachineMemOperand::MOStore) ? 1 : 0;
|
|
Addr.setReg(
|
|
constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx));
|
|
Addr.setOffsetReg(
|
|
constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1));
|
|
if (Addr.getOffsetReg()) {
|
|
assert(Addr.getOffset() == 0 && "Unexpected offset");
|
|
bool IsSigned = Addr.getExtendType() == AArch64_AM::SXTW ||
|
|
Addr.getExtendType() == AArch64_AM::SXTX;
|
|
MIB.addReg(Addr.getReg());
|
|
MIB.addReg(Addr.getOffsetReg());
|
|
MIB.addImm(IsSigned);
|
|
MIB.addImm(Addr.getShift() != 0);
|
|
} else {
|
|
MIB.addReg(Addr.getReg());
|
|
MIB.addImm(Offset);
|
|
}
|
|
}
|
|
|
|
if (MMO)
|
|
MIB.addMemOperand(MMO);
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitAddsSubs(bool UseAdds, MVT RetVT,
|
|
const Value *LHS, const Value *RHS,
|
|
bool IsZExt, bool WantResult) {
|
|
AArch64_AM::ShiftExtendType ExtendType = AArch64_AM::InvalidShiftExtend;
|
|
bool NeedExtend = false;
|
|
switch (RetVT.SimpleTy) {
|
|
default:
|
|
return 0;
|
|
case MVT::i1:
|
|
NeedExtend = true;
|
|
break;
|
|
case MVT::i8:
|
|
NeedExtend = true;
|
|
ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB;
|
|
break;
|
|
case MVT::i16:
|
|
NeedExtend = true;
|
|
ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
|
|
break;
|
|
case MVT::i32: // fall-through
|
|
case MVT::i64:
|
|
break;
|
|
}
|
|
MVT SrcVT = RetVT;
|
|
RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32);
|
|
|
|
// Canonicalize immediates to the RHS first.
|
|
if (UseAdds && isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
|
|
std::swap(LHS, RHS);
|
|
|
|
// Canonicalize shift immediate to the RHS.
|
|
if (UseAdds && isValueAvailable(LHS))
|
|
if (const auto *SI = dyn_cast<BinaryOperator>(LHS))
|
|
if (isa<ConstantInt>(SI->getOperand(1)))
|
|
if (SI->getOpcode() == Instruction::Shl ||
|
|
SI->getOpcode() == Instruction::LShr ||
|
|
SI->getOpcode() == Instruction::AShr )
|
|
std::swap(LHS, RHS);
|
|
|
|
unsigned LHSReg = getRegForValue(LHS);
|
|
if (!LHSReg)
|
|
return 0;
|
|
bool LHSIsKill = hasTrivialKill(LHS);
|
|
|
|
if (NeedExtend)
|
|
LHSReg = EmitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
|
|
|
|
unsigned ResultReg = 0;
|
|
if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
|
|
uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue();
|
|
if (C->isNegative())
|
|
ResultReg =
|
|
emitAddsSubs_ri(!UseAdds, RetVT, LHSReg, LHSIsKill, -Imm, WantResult);
|
|
else
|
|
ResultReg =
|
|
emitAddsSubs_ri(UseAdds, RetVT, LHSReg, LHSIsKill, Imm, WantResult);
|
|
}
|
|
if (ResultReg)
|
|
return ResultReg;
|
|
|
|
// Only extend the RHS within the instruction if there is a valid extend type.
|
|
if (ExtendType != AArch64_AM::InvalidShiftExtend && isValueAvailable(RHS)) {
|
|
if (const auto *SI = dyn_cast<BinaryOperator>(RHS))
|
|
if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1)))
|
|
if ((SI->getOpcode() == Instruction::Shl) && (C->getZExtValue() < 4)) {
|
|
unsigned RHSReg = getRegForValue(SI->getOperand(0));
|
|
if (!RHSReg)
|
|
return 0;
|
|
bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
|
|
return emitAddsSubs_rx(UseAdds, RetVT, LHSReg, LHSIsKill, RHSReg,
|
|
RHSIsKill, ExtendType, C->getZExtValue(),
|
|
WantResult);
|
|
}
|
|
unsigned RHSReg = getRegForValue(RHS);
|
|
if (!RHSReg)
|
|
return 0;
|
|
bool RHSIsKill = hasTrivialKill(RHS);
|
|
return emitAddsSubs_rx(UseAdds, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
|
|
ExtendType, 0, WantResult);
|
|
}
|
|
|
|
// Check if the shift can be folded into the instruction.
|
|
if (isValueAvailable(RHS))
|
|
if (const auto *SI = dyn_cast<BinaryOperator>(RHS)) {
|
|
if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1))) {
|
|
AArch64_AM::ShiftExtendType ShiftType = AArch64_AM::InvalidShiftExtend;
|
|
switch (SI->getOpcode()) {
|
|
default: break;
|
|
case Instruction::Shl: ShiftType = AArch64_AM::LSL; break;
|
|
case Instruction::LShr: ShiftType = AArch64_AM::LSR; break;
|
|
case Instruction::AShr: ShiftType = AArch64_AM::ASR; break;
|
|
}
|
|
uint64_t ShiftVal = C->getZExtValue();
|
|
if (ShiftType != AArch64_AM::InvalidShiftExtend) {
|
|
unsigned RHSReg = getRegForValue(SI->getOperand(0));
|
|
if (!RHSReg)
|
|
return 0;
|
|
bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
|
|
return emitAddsSubs_rs(UseAdds, RetVT, LHSReg, LHSIsKill, RHSReg,
|
|
RHSIsKill, ShiftType, ShiftVal, WantResult);
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned RHSReg = getRegForValue(RHS);
|
|
if (!RHSReg)
|
|
return 0;
|
|
bool RHSIsKill = hasTrivialKill(RHS);
|
|
|
|
if (NeedExtend)
|
|
RHSReg = EmitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
|
|
|
|
return emitAddsSubs_rr(UseAdds, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
|
|
WantResult);
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitAddsSubs_rr(bool UseAdds, MVT RetVT,
|
|
unsigned LHSReg, bool LHSIsKill,
|
|
unsigned RHSReg, bool RHSIsKill,
|
|
bool WantResult) {
|
|
assert(LHSReg && RHSReg && "Invalid register number.");
|
|
|
|
if (RetVT != MVT::i32 && RetVT != MVT::i64)
|
|
return 0;
|
|
|
|
static const unsigned OpcTable[2][2] = {
|
|
{ AArch64::ADDSWrr, AArch64::ADDSXrr },
|
|
{ AArch64::SUBSWrr, AArch64::SUBSXrr }
|
|
};
|
|
unsigned Opc = OpcTable[!UseAdds][(RetVT == MVT::i64)];
|
|
unsigned ResultReg;
|
|
if (WantResult) {
|
|
const TargetRegisterClass *RC =
|
|
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
ResultReg = createResultReg(RC);
|
|
} else
|
|
ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
|
|
|
|
const MCInstrDesc &II = TII.get(Opc);
|
|
LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
|
|
RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
|
|
.addReg(LHSReg, getKillRegState(LHSIsKill))
|
|
.addReg(RHSReg, getKillRegState(RHSIsKill));
|
|
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitAddsSubs_ri(bool UseAdds, MVT RetVT,
|
|
unsigned LHSReg, bool LHSIsKill,
|
|
uint64_t Imm, bool WantResult) {
|
|
assert(LHSReg && "Invalid register number.");
|
|
|
|
if (RetVT != MVT::i32 && RetVT != MVT::i64)
|
|
return 0;
|
|
|
|
unsigned ShiftImm;
|
|
if (isUInt<12>(Imm))
|
|
ShiftImm = 0;
|
|
else if ((Imm & 0xfff000) == Imm) {
|
|
ShiftImm = 12;
|
|
Imm >>= 12;
|
|
} else
|
|
return 0;
|
|
|
|
static const unsigned OpcTable[2][2] = {
|
|
{ AArch64::ADDSWri, AArch64::ADDSXri },
|
|
{ AArch64::SUBSWri, AArch64::SUBSXri }
|
|
};
|
|
unsigned Opc = OpcTable[!UseAdds][(RetVT == MVT::i64)];
|
|
unsigned ResultReg;
|
|
if (WantResult) {
|
|
const TargetRegisterClass *RC =
|
|
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
ResultReg = createResultReg(RC);
|
|
} else
|
|
ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
|
|
|
|
const MCInstrDesc &II = TII.get(Opc);
|
|
LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
|
|
.addReg(LHSReg, getKillRegState(LHSIsKill))
|
|
.addImm(Imm)
|
|
.addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
|
|
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT,
|
|
unsigned LHSReg, bool LHSIsKill,
|
|
unsigned RHSReg, bool RHSIsKill,
|
|
AArch64_AM::ShiftExtendType ShiftType,
|
|
uint64_t ShiftImm, bool WantResult) {
|
|
assert(LHSReg && RHSReg && "Invalid register number.");
|
|
|
|
if (RetVT != MVT::i32 && RetVT != MVT::i64)
|
|
return 0;
|
|
|
|
static const unsigned OpcTable[2][2] = {
|
|
{ AArch64::ADDWrs, AArch64::ADDXrs },
|
|
{ AArch64::SUBWrs, AArch64::SUBXrs }
|
|
};
|
|
unsigned Opc = OpcTable[!UseAdd][(RetVT == MVT::i64)];
|
|
unsigned ResultReg;
|
|
if (WantResult) {
|
|
const TargetRegisterClass *RC =
|
|
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
ResultReg = createResultReg(RC);
|
|
} else
|
|
ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
|
|
|
|
const MCInstrDesc &II = TII.get(Opc);
|
|
LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
|
|
RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
|
|
.addReg(LHSReg, getKillRegState(LHSIsKill))
|
|
.addReg(RHSReg, getKillRegState(RHSIsKill))
|
|
.addImm(getShifterImm(ShiftType, ShiftImm));
|
|
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitAddsSubs_rs(bool UseAdds, MVT RetVT,
|
|
unsigned LHSReg, bool LHSIsKill,
|
|
unsigned RHSReg, bool RHSIsKill,
|
|
AArch64_AM::ShiftExtendType ShiftType,
|
|
uint64_t ShiftImm, bool WantResult) {
|
|
assert(LHSReg && RHSReg && "Invalid register number.");
|
|
|
|
if (RetVT != MVT::i32 && RetVT != MVT::i64)
|
|
return 0;
|
|
|
|
static const unsigned OpcTable[2][2] = {
|
|
{ AArch64::ADDSWrs, AArch64::ADDSXrs },
|
|
{ AArch64::SUBSWrs, AArch64::SUBSXrs }
|
|
};
|
|
unsigned Opc = OpcTable[!UseAdds][(RetVT == MVT::i64)];
|
|
unsigned ResultReg;
|
|
if (WantResult) {
|
|
const TargetRegisterClass *RC =
|
|
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
ResultReg = createResultReg(RC);
|
|
} else
|
|
ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
|
|
|
|
const MCInstrDesc &II = TII.get(Opc);
|
|
LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
|
|
RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
|
|
.addReg(LHSReg, getKillRegState(LHSIsKill))
|
|
.addReg(RHSReg, getKillRegState(RHSIsKill))
|
|
.addImm(getShifterImm(ShiftType, ShiftImm));
|
|
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT,
|
|
unsigned LHSReg, bool LHSIsKill,
|
|
unsigned RHSReg, bool RHSIsKill,
|
|
AArch64_AM::ShiftExtendType ExtType,
|
|
uint64_t ShiftImm, bool WantResult) {
|
|
assert(LHSReg && RHSReg && "Invalid register number.");
|
|
|
|
if (RetVT != MVT::i32 && RetVT != MVT::i64)
|
|
return 0;
|
|
|
|
static const unsigned OpcTable[2][2] = {
|
|
{ AArch64::ADDWrx, AArch64::ADDXrx },
|
|
{ AArch64::SUBWrx, AArch64::SUBXrx }
|
|
};
|
|
unsigned Opc = OpcTable[!UseAdd][(RetVT == MVT::i64)];
|
|
unsigned ResultReg;
|
|
if (WantResult) {
|
|
const TargetRegisterClass *RC =
|
|
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
ResultReg = createResultReg(RC);
|
|
} else
|
|
ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
|
|
|
|
const MCInstrDesc &II = TII.get(Opc);
|
|
LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
|
|
RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
|
|
.addReg(LHSReg, getKillRegState(LHSIsKill))
|
|
.addReg(RHSReg, getKillRegState(RHSIsKill))
|
|
.addImm(getArithExtendImm(ExtType, ShiftImm));
|
|
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitAddsSubs_rx(bool UseAdds, MVT RetVT,
|
|
unsigned LHSReg, bool LHSIsKill,
|
|
unsigned RHSReg, bool RHSIsKill,
|
|
AArch64_AM::ShiftExtendType ExtType,
|
|
uint64_t ShiftImm, bool WantResult) {
|
|
assert(LHSReg && RHSReg && "Invalid register number.");
|
|
|
|
if (RetVT != MVT::i32 && RetVT != MVT::i64)
|
|
return 0;
|
|
|
|
static const unsigned OpcTable[2][2] = {
|
|
{ AArch64::ADDSWrx, AArch64::ADDSXrx },
|
|
{ AArch64::SUBSWrx, AArch64::SUBSXrx }
|
|
};
|
|
unsigned Opc = OpcTable[!UseAdds][(RetVT == MVT::i64)];
|
|
unsigned ResultReg;
|
|
if (WantResult) {
|
|
const TargetRegisterClass *RC =
|
|
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
ResultReg = createResultReg(RC);
|
|
} else
|
|
ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
|
|
|
|
const MCInstrDesc &II = TII.get(Opc);
|
|
LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
|
|
RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
|
|
.addReg(LHSReg, getKillRegState(LHSIsKill))
|
|
.addReg(RHSReg, getKillRegState(RHSIsKill))
|
|
.addImm(getArithExtendImm(ExtType, ShiftImm));
|
|
|
|
return ResultReg;
|
|
}
|
|
|
|
bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) {
|
|
Type *Ty = LHS->getType();
|
|
EVT EVT = TLI.getValueType(Ty, true);
|
|
if (!EVT.isSimple())
|
|
return false;
|
|
MVT VT = EVT.getSimpleVT();
|
|
|
|
switch (VT.SimpleTy) {
|
|
default:
|
|
return false;
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
case MVT::i64:
|
|
return emitICmp(VT, LHS, RHS, IsZExt);
|
|
case MVT::f32:
|
|
case MVT::f64:
|
|
return emitFCmp(VT, LHS, RHS);
|
|
}
|
|
}
|
|
|
|
bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS,
|
|
bool IsZExt) {
|
|
return emitSubs(RetVT, LHS, RHS, IsZExt, /*WantResult=*/false) != 0;
|
|
}
|
|
|
|
bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
|
|
uint64_t Imm) {
|
|
return emitAddsSubs_ri(false, RetVT, LHSReg, LHSIsKill, Imm,
|
|
/*WantResult=*/false) != 0;
|
|
}
|
|
|
|
bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) {
|
|
if (RetVT != MVT::f32 && RetVT != MVT::f64)
|
|
return false;
|
|
|
|
// Check to see if the 2nd operand is a constant that we can encode directly
|
|
// in the compare.
|
|
bool UseImm = false;
|
|
if (const auto *CFP = dyn_cast<ConstantFP>(RHS))
|
|
if (CFP->isZero() && !CFP->isNegative())
|
|
UseImm = true;
|
|
|
|
unsigned LHSReg = getRegForValue(LHS);
|
|
if (!LHSReg)
|
|
return false;
|
|
bool LHSIsKill = hasTrivialKill(LHS);
|
|
|
|
if (UseImm) {
|
|
unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri;
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
|
|
.addReg(LHSReg, getKillRegState(LHSIsKill));
|
|
return true;
|
|
}
|
|
|
|
unsigned RHSReg = getRegForValue(RHS);
|
|
if (!RHSReg)
|
|
return false;
|
|
bool RHSIsKill = hasTrivialKill(RHS);
|
|
|
|
unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr;
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
|
|
.addReg(LHSReg, getKillRegState(LHSIsKill))
|
|
.addReg(RHSReg, getKillRegState(RHSIsKill));
|
|
return true;
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitAdds(MVT RetVT, const Value *LHS,
|
|
const Value *RHS, bool IsZExt,
|
|
bool WantResult) {
|
|
return emitAddsSubs(true, RetVT, LHS, RHS, IsZExt, WantResult);
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitSubs(MVT RetVT, const Value *LHS,
|
|
const Value *RHS, bool IsZExt,
|
|
bool WantResult) {
|
|
return emitAddsSubs(false, RetVT, LHS, RHS, IsZExt, WantResult);
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,
|
|
bool LHSIsKill, unsigned RHSReg,
|
|
bool RHSIsKill, bool WantResult) {
|
|
return emitAddsSubs_rr(false, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
|
|
WantResult);
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
|
|
bool LHSIsKill, unsigned RHSReg,
|
|
bool RHSIsKill,
|
|
AArch64_AM::ShiftExtendType ShiftType,
|
|
uint64_t ShiftImm, bool WantResult) {
|
|
return emitAddsSubs_rs(false, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
|
|
ShiftType, ShiftImm, WantResult);
|
|
}
|
|
|
|
// FIXME: This should be eventually generated automatically by tblgen.
|
|
unsigned AArch64FastISel::emitAND_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
|
|
uint64_t Imm) {
|
|
const TargetRegisterClass *RC = nullptr;
|
|
unsigned Opc = 0;
|
|
unsigned RegSize = 0;
|
|
switch (RetVT.SimpleTy) {
|
|
default:
|
|
return 0;
|
|
case MVT::i32:
|
|
Opc = AArch64::ANDWri;
|
|
RC = &AArch64::GPR32spRegClass;
|
|
RegSize = 32;
|
|
break;
|
|
case MVT::i64:
|
|
Opc = AArch64::ANDXri;
|
|
RC = &AArch64::GPR64spRegClass;
|
|
RegSize = 64;
|
|
break;
|
|
}
|
|
|
|
if (!AArch64_AM::isLogicalImmediate(Imm, RegSize))
|
|
return 0;
|
|
|
|
return FastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill,
|
|
AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
|
|
}
|
|
|
|
bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
|
|
MachineMemOperand *MMO) {
|
|
// Simplify this down to something we can handle.
|
|
if (!SimplifyAddress(Addr, VT))
|
|
return false;
|
|
|
|
unsigned ScaleFactor;
|
|
switch (VT.SimpleTy) {
|
|
default: llvm_unreachable("Unexpected value type.");
|
|
case MVT::i1: // fall-through
|
|
case MVT::i8: ScaleFactor = 1; break;
|
|
case MVT::i16: ScaleFactor = 2; break;
|
|
case MVT::i32: // fall-through
|
|
case MVT::f32: ScaleFactor = 4; break;
|
|
case MVT::i64: // fall-through
|
|
case MVT::f64: ScaleFactor = 8; break;
|
|
}
|
|
|
|
// Negative offsets require unscaled, 9-bit, signed immediate offsets.
|
|
// Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
|
|
bool UseScaled = true;
|
|
if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
|
|
UseScaled = false;
|
|
ScaleFactor = 1;
|
|
}
|
|
|
|
static const unsigned OpcTable[4][6] = {
|
|
{ AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi, AArch64::LDURXi,
|
|
AArch64::LDURSi, AArch64::LDURDi },
|
|
{ AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui, AArch64::LDRXui,
|
|
AArch64::LDRSui, AArch64::LDRDui },
|
|
{ AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX, AArch64::LDRXroX,
|
|
AArch64::LDRSroX, AArch64::LDRDroX },
|
|
{ AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW, AArch64::LDRXroW,
|
|
AArch64::LDRSroW, AArch64::LDRDroW }
|
|
};
|
|
|
|
unsigned Opc;
|
|
const TargetRegisterClass *RC;
|
|
bool VTIsi1 = false;
|
|
bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
|
|
Addr.getOffsetReg();
|
|
unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
|
|
if (Addr.getExtendType() == AArch64_AM::UXTW ||
|
|
Addr.getExtendType() == AArch64_AM::SXTW)
|
|
Idx++;
|
|
|
|
switch (VT.SimpleTy) {
|
|
default: llvm_unreachable("Unexpected value type.");
|
|
case MVT::i1: VTIsi1 = true; // Intentional fall-through.
|
|
case MVT::i8: Opc = OpcTable[Idx][0]; RC = &AArch64::GPR32RegClass; break;
|
|
case MVT::i16: Opc = OpcTable[Idx][1]; RC = &AArch64::GPR32RegClass; break;
|
|
case MVT::i32: Opc = OpcTable[Idx][2]; RC = &AArch64::GPR32RegClass; break;
|
|
case MVT::i64: Opc = OpcTable[Idx][3]; RC = &AArch64::GPR64RegClass; break;
|
|
case MVT::f32: Opc = OpcTable[Idx][4]; RC = &AArch64::FPR32RegClass; break;
|
|
case MVT::f64: Opc = OpcTable[Idx][5]; RC = &AArch64::FPR64RegClass; break;
|
|
}
|
|
|
|
// Create the base instruction, then add the operands.
|
|
ResultReg = createResultReg(RC);
|
|
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(Opc), ResultReg);
|
|
AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, ScaleFactor, MMO);
|
|
|
|
// Loading an i1 requires special handling.
|
|
if (VTIsi1) {
|
|
unsigned ANDReg = emitAND_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);
|
|
assert(ANDReg && "Unexpected AND instruction emission failure.");
|
|
ResultReg = ANDReg;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectLoad(const Instruction *I) {
|
|
MVT VT;
|
|
// Verify we have a legal type before going any further. Currently, we handle
|
|
// simple types that will directly fit in a register (i32/f32/i64/f64) or
|
|
// those that can be sign or zero-extended to a basic operation (i1/i8/i16).
|
|
if (!isLoadStoreTypeLegal(I->getType(), VT) || cast<LoadInst>(I)->isAtomic())
|
|
return false;
|
|
|
|
// See if we can handle this address.
|
|
Address Addr;
|
|
if (!ComputeAddress(I->getOperand(0), Addr, I->getType()))
|
|
return false;
|
|
|
|
unsigned ResultReg;
|
|
if (!EmitLoad(VT, ResultReg, Addr, createMachineMemOperandFor(I)))
|
|
return false;
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
|
|
MachineMemOperand *MMO) {
|
|
// Simplify this down to something we can handle.
|
|
if (!SimplifyAddress(Addr, VT))
|
|
return false;
|
|
|
|
unsigned ScaleFactor;
|
|
switch (VT.SimpleTy) {
|
|
default: llvm_unreachable("Unexpected value type.");
|
|
case MVT::i1: // fall-through
|
|
case MVT::i8: ScaleFactor = 1; break;
|
|
case MVT::i16: ScaleFactor = 2; break;
|
|
case MVT::i32: // fall-through
|
|
case MVT::f32: ScaleFactor = 4; break;
|
|
case MVT::i64: // fall-through
|
|
case MVT::f64: ScaleFactor = 8; break;
|
|
}
|
|
|
|
// Negative offsets require unscaled, 9-bit, signed immediate offsets.
|
|
// Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
|
|
bool UseScaled = true;
|
|
if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
|
|
UseScaled = false;
|
|
ScaleFactor = 1;
|
|
}
|
|
|
|
|
|
static const unsigned OpcTable[4][6] = {
|
|
{ AArch64::STURBBi, AArch64::STURHHi, AArch64::STURWi, AArch64::STURXi,
|
|
AArch64::STURSi, AArch64::STURDi },
|
|
{ AArch64::STRBBui, AArch64::STRHHui, AArch64::STRWui, AArch64::STRXui,
|
|
AArch64::STRSui, AArch64::STRDui },
|
|
{ AArch64::STRBBroX, AArch64::STRHHroX, AArch64::STRWroX, AArch64::STRXroX,
|
|
AArch64::STRSroX, AArch64::STRDroX },
|
|
{ AArch64::STRBBroW, AArch64::STRHHroW, AArch64::STRWroW, AArch64::STRXroW,
|
|
AArch64::STRSroW, AArch64::STRDroW }
|
|
|
|
};
|
|
|
|
unsigned Opc;
|
|
bool VTIsi1 = false;
|
|
bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
|
|
Addr.getOffsetReg();
|
|
unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
|
|
if (Addr.getExtendType() == AArch64_AM::UXTW ||
|
|
Addr.getExtendType() == AArch64_AM::SXTW)
|
|
Idx++;
|
|
|
|
switch (VT.SimpleTy) {
|
|
default: llvm_unreachable("Unexpected value type.");
|
|
case MVT::i1: VTIsi1 = true;
|
|
case MVT::i8: Opc = OpcTable[Idx][0]; break;
|
|
case MVT::i16: Opc = OpcTable[Idx][1]; break;
|
|
case MVT::i32: Opc = OpcTable[Idx][2]; break;
|
|
case MVT::i64: Opc = OpcTable[Idx][3]; break;
|
|
case MVT::f32: Opc = OpcTable[Idx][4]; break;
|
|
case MVT::f64: Opc = OpcTable[Idx][5]; break;
|
|
}
|
|
|
|
// Storing an i1 requires special handling.
|
|
if (VTIsi1 && SrcReg != AArch64::WZR) {
|
|
unsigned ANDReg = emitAND_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
|
|
assert(ANDReg && "Unexpected AND instruction emission failure.");
|
|
SrcReg = ANDReg;
|
|
}
|
|
// Create the base instruction, then add the operands.
|
|
const MCInstrDesc &II = TII.get(Opc);
|
|
SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
|
|
MachineInstrBuilder MIB =
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(SrcReg);
|
|
AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, ScaleFactor, MMO);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectStore(const Instruction *I) {
|
|
MVT VT;
|
|
const Value *Op0 = I->getOperand(0);
|
|
// Verify we have a legal type before going any further. Currently, we handle
|
|
// simple types that will directly fit in a register (i32/f32/i64/f64) or
|
|
// those that can be sign or zero-extended to a basic operation (i1/i8/i16).
|
|
if (!isLoadStoreTypeLegal(Op0->getType(), VT) ||
|
|
cast<StoreInst>(I)->isAtomic())
|
|
return false;
|
|
|
|
// Get the value to be stored into a register. Use the zero register directly
|
|
// when possible to avoid an unnecessary copy and a wasted register.
|
|
unsigned SrcReg = 0;
|
|
if (const auto *CI = dyn_cast<ConstantInt>(Op0)) {
|
|
if (CI->isZero())
|
|
SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
|
|
} else if (const auto *CF = dyn_cast<ConstantFP>(Op0)) {
|
|
if (CF->isZero() && !CF->isNegative()) {
|
|
VT = MVT::getIntegerVT(VT.getSizeInBits());
|
|
SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
|
|
}
|
|
}
|
|
|
|
if (!SrcReg)
|
|
SrcReg = getRegForValue(Op0);
|
|
|
|
if (!SrcReg)
|
|
return false;
|
|
|
|
// See if we can handle this address.
|
|
Address Addr;
|
|
if (!ComputeAddress(I->getOperand(1), Addr, I->getOperand(0)->getType()))
|
|
return false;
|
|
|
|
if (!EmitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I)))
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
|
|
switch (Pred) {
|
|
case CmpInst::FCMP_ONE:
|
|
case CmpInst::FCMP_UEQ:
|
|
default:
|
|
// AL is our "false" for now. The other two need more compares.
|
|
return AArch64CC::AL;
|
|
case CmpInst::ICMP_EQ:
|
|
case CmpInst::FCMP_OEQ:
|
|
return AArch64CC::EQ;
|
|
case CmpInst::ICMP_SGT:
|
|
case CmpInst::FCMP_OGT:
|
|
return AArch64CC::GT;
|
|
case CmpInst::ICMP_SGE:
|
|
case CmpInst::FCMP_OGE:
|
|
return AArch64CC::GE;
|
|
case CmpInst::ICMP_UGT:
|
|
case CmpInst::FCMP_UGT:
|
|
return AArch64CC::HI;
|
|
case CmpInst::FCMP_OLT:
|
|
return AArch64CC::MI;
|
|
case CmpInst::ICMP_ULE:
|
|
case CmpInst::FCMP_OLE:
|
|
return AArch64CC::LS;
|
|
case CmpInst::FCMP_ORD:
|
|
return AArch64CC::VC;
|
|
case CmpInst::FCMP_UNO:
|
|
return AArch64CC::VS;
|
|
case CmpInst::FCMP_UGE:
|
|
return AArch64CC::PL;
|
|
case CmpInst::ICMP_SLT:
|
|
case CmpInst::FCMP_ULT:
|
|
return AArch64CC::LT;
|
|
case CmpInst::ICMP_SLE:
|
|
case CmpInst::FCMP_ULE:
|
|
return AArch64CC::LE;
|
|
case CmpInst::FCMP_UNE:
|
|
case CmpInst::ICMP_NE:
|
|
return AArch64CC::NE;
|
|
case CmpInst::ICMP_UGE:
|
|
return AArch64CC::HS;
|
|
case CmpInst::ICMP_ULT:
|
|
return AArch64CC::LO;
|
|
}
|
|
}
|
|
|
|
bool AArch64FastISel::SelectBranch(const Instruction *I) {
|
|
const BranchInst *BI = cast<BranchInst>(I);
|
|
MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
|
|
MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
|
|
|
|
AArch64CC::CondCode CC = AArch64CC::NE;
|
|
if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
|
|
if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
|
|
// We may not handle every CC for now.
|
|
CC = getCompareCC(CI->getPredicate());
|
|
if (CC == AArch64CC::AL)
|
|
return false;
|
|
|
|
// Emit the cmp.
|
|
if (!emitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
|
|
return false;
|
|
|
|
// Emit the branch.
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
|
|
.addImm(CC)
|
|
.addMBB(TBB);
|
|
|
|
// Obtain the branch weight and add the TrueBB to the successor list.
|
|
uint32_t BranchWeight = 0;
|
|
if (FuncInfo.BPI)
|
|
BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
|
|
TBB->getBasicBlock());
|
|
FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
|
|
|
|
FastEmitBranch(FBB, DbgLoc);
|
|
return true;
|
|
}
|
|
} else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
|
|
MVT SrcVT;
|
|
if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
|
|
(isLoadStoreTypeLegal(TI->getOperand(0)->getType(), SrcVT))) {
|
|
unsigned CondReg = getRegForValue(TI->getOperand(0));
|
|
if (!CondReg)
|
|
return false;
|
|
bool CondIsKill = hasTrivialKill(TI->getOperand(0));
|
|
|
|
// Issue an extract_subreg to get the lower 32-bits.
|
|
if (SrcVT == MVT::i64) {
|
|
CondReg = FastEmitInst_extractsubreg(MVT::i32, CondReg, CondIsKill,
|
|
AArch64::sub_32);
|
|
CondIsKill = true;
|
|
}
|
|
|
|
unsigned ANDReg = emitAND_ri(MVT::i32, CondReg, CondIsKill, 1);
|
|
assert(ANDReg && "Unexpected AND instruction emission failure.");
|
|
emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
|
|
|
|
if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
|
|
std::swap(TBB, FBB);
|
|
CC = AArch64CC::EQ;
|
|
}
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
|
|
.addImm(CC)
|
|
.addMBB(TBB);
|
|
|
|
// Obtain the branch weight and add the TrueBB to the successor list.
|
|
uint32_t BranchWeight = 0;
|
|
if (FuncInfo.BPI)
|
|
BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
|
|
TBB->getBasicBlock());
|
|
FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
|
|
|
|
FastEmitBranch(FBB, DbgLoc);
|
|
return true;
|
|
}
|
|
} else if (const ConstantInt *CI =
|
|
dyn_cast<ConstantInt>(BI->getCondition())) {
|
|
uint64_t Imm = CI->getZExtValue();
|
|
MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
|
|
.addMBB(Target);
|
|
|
|
// Obtain the branch weight and add the target to the successor list.
|
|
uint32_t BranchWeight = 0;
|
|
if (FuncInfo.BPI)
|
|
BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
|
|
Target->getBasicBlock());
|
|
FuncInfo.MBB->addSuccessor(Target, BranchWeight);
|
|
return true;
|
|
} else if (foldXALUIntrinsic(CC, I, BI->getCondition())) {
|
|
// Fake request the condition, otherwise the intrinsic might be completely
|
|
// optimized away.
|
|
unsigned CondReg = getRegForValue(BI->getCondition());
|
|
if (!CondReg)
|
|
return false;
|
|
|
|
// Emit the branch.
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
|
|
.addImm(CC)
|
|
.addMBB(TBB);
|
|
|
|
// Obtain the branch weight and add the TrueBB to the successor list.
|
|
uint32_t BranchWeight = 0;
|
|
if (FuncInfo.BPI)
|
|
BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
|
|
TBB->getBasicBlock());
|
|
FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
|
|
|
|
FastEmitBranch(FBB, DbgLoc);
|
|
return true;
|
|
}
|
|
|
|
unsigned CondReg = getRegForValue(BI->getCondition());
|
|
if (CondReg == 0)
|
|
return false;
|
|
bool CondRegIsKill = hasTrivialKill(BI->getCondition());
|
|
|
|
// We've been divorced from our compare! Our block was split, and
|
|
// now our compare lives in a predecessor block. We musn't
|
|
// re-compare here, as the children of the compare aren't guaranteed
|
|
// live across the block boundary (we *could* check for this).
|
|
// Regardless, the compare has been done in the predecessor block,
|
|
// and it left a value for us in a virtual register. Ergo, we test
|
|
// the one-bit value left in the virtual register.
|
|
emitICmp_ri(MVT::i32, CondReg, CondRegIsKill, 0);
|
|
|
|
if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
|
|
std::swap(TBB, FBB);
|
|
CC = AArch64CC::EQ;
|
|
}
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
|
|
.addImm(CC)
|
|
.addMBB(TBB);
|
|
|
|
// Obtain the branch weight and add the TrueBB to the successor list.
|
|
uint32_t BranchWeight = 0;
|
|
if (FuncInfo.BPI)
|
|
BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
|
|
TBB->getBasicBlock());
|
|
FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
|
|
|
|
FastEmitBranch(FBB, DbgLoc);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectIndirectBr(const Instruction *I) {
|
|
const IndirectBrInst *BI = cast<IndirectBrInst>(I);
|
|
unsigned AddrReg = getRegForValue(BI->getOperand(0));
|
|
if (AddrReg == 0)
|
|
return false;
|
|
|
|
// Emit the indirect branch.
|
|
const MCInstrDesc &II = TII.get(AArch64::BR);
|
|
AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs());
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(AddrReg);
|
|
|
|
// Make sure the CFG is up-to-date.
|
|
for (unsigned i = 0, e = BI->getNumSuccessors(); i != e; ++i)
|
|
FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[BI->getSuccessor(i)]);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectCmp(const Instruction *I) {
|
|
const CmpInst *CI = cast<CmpInst>(I);
|
|
|
|
// We may not handle every CC for now.
|
|
AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
|
|
if (CC == AArch64CC::AL)
|
|
return false;
|
|
|
|
// Emit the cmp.
|
|
if (!emitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
|
|
return false;
|
|
|
|
// Now set a register based on the comparison.
|
|
AArch64CC::CondCode invertedCC = getInvertedCondCode(CC);
|
|
unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
|
|
ResultReg)
|
|
.addReg(AArch64::WZR)
|
|
.addReg(AArch64::WZR)
|
|
.addImm(invertedCC);
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectSelect(const Instruction *I) {
|
|
const SelectInst *SI = cast<SelectInst>(I);
|
|
|
|
EVT DestEVT = TLI.getValueType(SI->getType(), true);
|
|
if (!DestEVT.isSimple())
|
|
return false;
|
|
|
|
MVT DestVT = DestEVT.getSimpleVT();
|
|
if (DestVT != MVT::i32 && DestVT != MVT::i64 && DestVT != MVT::f32 &&
|
|
DestVT != MVT::f64)
|
|
return false;
|
|
|
|
unsigned SelectOpc;
|
|
const TargetRegisterClass *RC = nullptr;
|
|
switch (DestVT.SimpleTy) {
|
|
default: return false;
|
|
case MVT::i32:
|
|
SelectOpc = AArch64::CSELWr; RC = &AArch64::GPR32RegClass; break;
|
|
case MVT::i64:
|
|
SelectOpc = AArch64::CSELXr; RC = &AArch64::GPR64RegClass; break;
|
|
case MVT::f32:
|
|
SelectOpc = AArch64::FCSELSrrr; RC = &AArch64::FPR32RegClass; break;
|
|
case MVT::f64:
|
|
SelectOpc = AArch64::FCSELDrrr; RC = &AArch64::FPR64RegClass; break;
|
|
}
|
|
|
|
const Value *Cond = SI->getCondition();
|
|
bool NeedTest = true;
|
|
AArch64CC::CondCode CC = AArch64CC::NE;
|
|
if (foldXALUIntrinsic(CC, I, Cond))
|
|
NeedTest = false;
|
|
|
|
unsigned CondReg = getRegForValue(Cond);
|
|
if (!CondReg)
|
|
return false;
|
|
bool CondIsKill = hasTrivialKill(Cond);
|
|
|
|
if (NeedTest) {
|
|
unsigned ANDReg = emitAND_ri(MVT::i32, CondReg, CondIsKill, 1);
|
|
assert(ANDReg && "Unexpected AND instruction emission failure.");
|
|
emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
|
|
}
|
|
|
|
unsigned TrueReg = getRegForValue(SI->getTrueValue());
|
|
bool TrueIsKill = hasTrivialKill(SI->getTrueValue());
|
|
|
|
unsigned FalseReg = getRegForValue(SI->getFalseValue());
|
|
bool FalseIsKill = hasTrivialKill(SI->getFalseValue());
|
|
|
|
if (!TrueReg || !FalseReg)
|
|
return false;
|
|
|
|
unsigned ResultReg = FastEmitInst_rri(SelectOpc, RC, TrueReg, TrueIsKill,
|
|
FalseReg, FalseIsKill, CC);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectFPExt(const Instruction *I) {
|
|
Value *V = I->getOperand(0);
|
|
if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy())
|
|
return false;
|
|
|
|
unsigned Op = getRegForValue(V);
|
|
if (Op == 0)
|
|
return false;
|
|
|
|
unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
|
|
ResultReg).addReg(Op);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectFPTrunc(const Instruction *I) {
|
|
Value *V = I->getOperand(0);
|
|
if (!I->getType()->isFloatTy() || !V->getType()->isDoubleTy())
|
|
return false;
|
|
|
|
unsigned Op = getRegForValue(V);
|
|
if (Op == 0)
|
|
return false;
|
|
|
|
unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
|
|
ResultReg).addReg(Op);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
// FPToUI and FPToSI
|
|
bool AArch64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
|
|
MVT DestVT;
|
|
if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
|
|
return false;
|
|
|
|
unsigned SrcReg = getRegForValue(I->getOperand(0));
|
|
if (SrcReg == 0)
|
|
return false;
|
|
|
|
EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
|
|
if (SrcVT == MVT::f128)
|
|
return false;
|
|
|
|
unsigned Opc;
|
|
if (SrcVT == MVT::f64) {
|
|
if (Signed)
|
|
Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
|
|
else
|
|
Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
|
|
} else {
|
|
if (Signed)
|
|
Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
|
|
else
|
|
Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
|
|
}
|
|
unsigned ResultReg = createResultReg(
|
|
DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
|
|
.addReg(SrcReg);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
|
|
MVT DestVT;
|
|
if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
|
|
return false;
|
|
assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
|
|
"Unexpected value type.");
|
|
|
|
unsigned SrcReg = getRegForValue(I->getOperand(0));
|
|
if (!SrcReg)
|
|
return false;
|
|
bool SrcIsKill = hasTrivialKill(I->getOperand(0));
|
|
|
|
EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
|
|
|
|
// Handle sign-extension.
|
|
if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
|
|
SrcReg =
|
|
EmitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
|
|
if (!SrcReg)
|
|
return false;
|
|
SrcIsKill = true;
|
|
}
|
|
|
|
unsigned Opc;
|
|
if (SrcVT == MVT::i64) {
|
|
if (Signed)
|
|
Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
|
|
else
|
|
Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
|
|
} else {
|
|
if (Signed)
|
|
Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
|
|
else
|
|
Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
|
|
}
|
|
|
|
unsigned ResultReg = FastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,
|
|
SrcIsKill);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::FastLowerArguments() {
|
|
if (!FuncInfo.CanLowerReturn)
|
|
return false;
|
|
|
|
const Function *F = FuncInfo.Fn;
|
|
if (F->isVarArg())
|
|
return false;
|
|
|
|
CallingConv::ID CC = F->getCallingConv();
|
|
if (CC != CallingConv::C)
|
|
return false;
|
|
|
|
// Only handle simple cases like i1/i8/i16/i32/i64/f32/f64 of up to 8 GPR and
|
|
// FPR each.
|
|
unsigned GPRCnt = 0;
|
|
unsigned FPRCnt = 0;
|
|
unsigned Idx = 0;
|
|
for (auto const &Arg : F->args()) {
|
|
// The first argument is at index 1.
|
|
++Idx;
|
|
if (F->getAttributes().hasAttribute(Idx, Attribute::ByVal) ||
|
|
F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
|
|
F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
|
|
F->getAttributes().hasAttribute(Idx, Attribute::Nest))
|
|
return false;
|
|
|
|
Type *ArgTy = Arg.getType();
|
|
if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
|
|
return false;
|
|
|
|
EVT ArgVT = TLI.getValueType(ArgTy);
|
|
if (!ArgVT.isSimple()) return false;
|
|
switch (ArgVT.getSimpleVT().SimpleTy) {
|
|
default: return false;
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
case MVT::i64:
|
|
++GPRCnt;
|
|
break;
|
|
case MVT::f16:
|
|
case MVT::f32:
|
|
case MVT::f64:
|
|
++FPRCnt;
|
|
break;
|
|
}
|
|
|
|
if (GPRCnt > 8 || FPRCnt > 8)
|
|
return false;
|
|
}
|
|
|
|
static const MCPhysReg Registers[5][8] = {
|
|
{ AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
|
|
AArch64::W5, AArch64::W6, AArch64::W7 },
|
|
{ AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
|
|
AArch64::X5, AArch64::X6, AArch64::X7 },
|
|
{ AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
|
|
AArch64::H5, AArch64::H6, AArch64::H7 },
|
|
{ AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
|
|
AArch64::S5, AArch64::S6, AArch64::S7 },
|
|
{ AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
|
|
AArch64::D5, AArch64::D6, AArch64::D7 }
|
|
};
|
|
|
|
unsigned GPRIdx = 0;
|
|
unsigned FPRIdx = 0;
|
|
for (auto const &Arg : F->args()) {
|
|
MVT VT = TLI.getSimpleValueType(Arg.getType());
|
|
unsigned SrcReg;
|
|
const TargetRegisterClass *RC = nullptr;
|
|
switch (VT.SimpleTy) {
|
|
default: llvm_unreachable("Unexpected value type.");
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16: VT = MVT::i32; // fall-through
|
|
case MVT::i32:
|
|
SrcReg = Registers[0][GPRIdx++]; RC = &AArch64::GPR32RegClass; break;
|
|
case MVT::i64:
|
|
SrcReg = Registers[1][GPRIdx++]; RC = &AArch64::GPR64RegClass; break;
|
|
case MVT::f16:
|
|
SrcReg = Registers[2][FPRIdx++]; RC = &AArch64::FPR16RegClass; break;
|
|
case MVT::f32:
|
|
SrcReg = Registers[3][FPRIdx++]; RC = &AArch64::FPR32RegClass; break;
|
|
case MVT::f64:
|
|
SrcReg = Registers[4][FPRIdx++]; RC = &AArch64::FPR64RegClass; break;
|
|
}
|
|
|
|
// Skip unused arguments.
|
|
if (Arg.use_empty()) {
|
|
UpdateValueMap(&Arg, 0);
|
|
continue;
|
|
}
|
|
|
|
unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
|
|
// FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
|
|
// Without this, EmitLiveInCopies may eliminate the livein if its only
|
|
// use is a bitcast (which isn't turned into an instruction).
|
|
unsigned ResultReg = createResultReg(RC);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(TargetOpcode::COPY), ResultReg)
|
|
.addReg(DstReg, getKillRegState(true));
|
|
UpdateValueMap(&Arg, ResultReg);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::ProcessCallArgs(CallLoweringInfo &CLI,
|
|
SmallVectorImpl<MVT> &OutVTs,
|
|
unsigned &NumBytes) {
|
|
CallingConv::ID CC = CLI.CallConv;
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
|
CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
|
|
CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
|
|
|
|
// Get a count of how many bytes are to be pushed on the stack.
|
|
NumBytes = CCInfo.getNextStackOffset();
|
|
|
|
// Issue CALLSEQ_START
|
|
unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
|
|
.addImm(NumBytes);
|
|
|
|
// Process the args.
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
CCValAssign &VA = ArgLocs[i];
|
|
const Value *ArgVal = CLI.OutVals[VA.getValNo()];
|
|
MVT ArgVT = OutVTs[VA.getValNo()];
|
|
|
|
unsigned ArgReg = getRegForValue(ArgVal);
|
|
if (!ArgReg)
|
|
return false;
|
|
|
|
// Handle arg promotion: SExt, ZExt, AExt.
|
|
switch (VA.getLocInfo()) {
|
|
case CCValAssign::Full:
|
|
break;
|
|
case CCValAssign::SExt: {
|
|
MVT DestVT = VA.getLocVT();
|
|
MVT SrcVT = ArgVT;
|
|
ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
|
|
if (!ArgReg)
|
|
return false;
|
|
break;
|
|
}
|
|
case CCValAssign::AExt:
|
|
// Intentional fall-through.
|
|
case CCValAssign::ZExt: {
|
|
MVT DestVT = VA.getLocVT();
|
|
MVT SrcVT = ArgVT;
|
|
ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
|
|
if (!ArgReg)
|
|
return false;
|
|
break;
|
|
}
|
|
default:
|
|
llvm_unreachable("Unknown arg promotion!");
|
|
}
|
|
|
|
// Now copy/store arg to correct locations.
|
|
if (VA.isRegLoc() && !VA.needsCustom()) {
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
|
|
CLI.OutRegs.push_back(VA.getLocReg());
|
|
} else if (VA.needsCustom()) {
|
|
// FIXME: Handle custom args.
|
|
return false;
|
|
} else {
|
|
assert(VA.isMemLoc() && "Assuming store on stack.");
|
|
|
|
// Don't emit stores for undef values.
|
|
if (isa<UndefValue>(ArgVal))
|
|
continue;
|
|
|
|
// Need to store on the stack.
|
|
unsigned ArgSize = (ArgVT.getSizeInBits() + 7) / 8;
|
|
|
|
unsigned BEAlign = 0;
|
|
if (ArgSize < 8 && !Subtarget->isLittleEndian())
|
|
BEAlign = 8 - ArgSize;
|
|
|
|
Address Addr;
|
|
Addr.setKind(Address::RegBase);
|
|
Addr.setReg(AArch64::SP);
|
|
Addr.setOffset(VA.getLocMemOffset() + BEAlign);
|
|
|
|
unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
|
|
MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
|
|
MachinePointerInfo::getStack(Addr.getOffset()),
|
|
MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
|
|
|
|
if (!EmitStore(ArgVT, ArgReg, Addr, MMO))
|
|
return false;
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::FinishCall(CallLoweringInfo &CLI, MVT RetVT,
|
|
unsigned NumBytes) {
|
|
CallingConv::ID CC = CLI.CallConv;
|
|
|
|
// Issue CALLSEQ_END
|
|
unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
|
|
.addImm(NumBytes).addImm(0);
|
|
|
|
// Now the return value.
|
|
if (RetVT != MVT::isVoid) {
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
|
|
CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
|
|
|
|
// Only handle a single return value.
|
|
if (RVLocs.size() != 1)
|
|
return false;
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
MVT CopyVT = RVLocs[0].getValVT();
|
|
unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(TargetOpcode::COPY), ResultReg)
|
|
.addReg(RVLocs[0].getLocReg());
|
|
CLI.InRegs.push_back(RVLocs[0].getLocReg());
|
|
|
|
CLI.ResultReg = ResultReg;
|
|
CLI.NumResultRegs = 1;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::FastLowerCall(CallLoweringInfo &CLI) {
|
|
CallingConv::ID CC = CLI.CallConv;
|
|
bool IsTailCall = CLI.IsTailCall;
|
|
bool IsVarArg = CLI.IsVarArg;
|
|
const Value *Callee = CLI.Callee;
|
|
const char *SymName = CLI.SymName;
|
|
|
|
// Allow SelectionDAG isel to handle tail calls.
|
|
if (IsTailCall)
|
|
return false;
|
|
|
|
CodeModel::Model CM = TM.getCodeModel();
|
|
// Only support the small and large code model.
|
|
if (CM != CodeModel::Small && CM != CodeModel::Large)
|
|
return false;
|
|
|
|
// FIXME: Add large code model support for ELF.
|
|
if (CM == CodeModel::Large && !Subtarget->isTargetMachO())
|
|
return false;
|
|
|
|
// Let SDISel handle vararg functions.
|
|
if (IsVarArg)
|
|
return false;
|
|
|
|
// FIXME: Only handle *simple* calls for now.
|
|
MVT RetVT;
|
|
if (CLI.RetTy->isVoidTy())
|
|
RetVT = MVT::isVoid;
|
|
else if (!isTypeLegal(CLI.RetTy, RetVT))
|
|
return false;
|
|
|
|
for (auto Flag : CLI.OutFlags)
|
|
if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
|
|
return false;
|
|
|
|
// Set up the argument vectors.
|
|
SmallVector<MVT, 16> OutVTs;
|
|
OutVTs.reserve(CLI.OutVals.size());
|
|
|
|
for (auto *Val : CLI.OutVals) {
|
|
MVT VT;
|
|
if (!isTypeLegal(Val->getType(), VT) &&
|
|
!(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
|
|
return false;
|
|
|
|
// We don't handle vector parameters yet.
|
|
if (VT.isVector() || VT.getSizeInBits() > 64)
|
|
return false;
|
|
|
|
OutVTs.push_back(VT);
|
|
}
|
|
|
|
Address Addr;
|
|
if (!ComputeCallAddress(Callee, Addr))
|
|
return false;
|
|
|
|
// Handle the arguments now that we've gotten them.
|
|
unsigned NumBytes;
|
|
if (!ProcessCallArgs(CLI, OutVTs, NumBytes))
|
|
return false;
|
|
|
|
// Issue the call.
|
|
MachineInstrBuilder MIB;
|
|
if (CM == CodeModel::Small) {
|
|
const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL);
|
|
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II);
|
|
if (SymName)
|
|
MIB.addExternalSymbol(SymName, 0);
|
|
else if (Addr.getGlobalValue())
|
|
MIB.addGlobalAddress(Addr.getGlobalValue(), 0, 0);
|
|
else if (Addr.getReg()) {
|
|
unsigned Reg = constrainOperandRegClass(II, Addr.getReg(), 0);
|
|
MIB.addReg(Reg);
|
|
} else
|
|
return false;
|
|
} else {
|
|
unsigned CallReg = 0;
|
|
if (SymName) {
|
|
unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
|
|
ADRPReg)
|
|
.addExternalSymbol(SymName, AArch64II::MO_GOT | AArch64II::MO_PAGE);
|
|
|
|
CallReg = createResultReg(&AArch64::GPR64RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
|
|
CallReg)
|
|
.addReg(ADRPReg)
|
|
.addExternalSymbol(SymName, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
|
|
AArch64II::MO_NC);
|
|
} else if (Addr.getGlobalValue()) {
|
|
CallReg = AArch64MaterializeGV(Addr.getGlobalValue());
|
|
} else if (Addr.getReg())
|
|
CallReg = Addr.getReg();
|
|
|
|
if (!CallReg)
|
|
return false;
|
|
|
|
const MCInstrDesc &II = TII.get(AArch64::BLR);
|
|
CallReg = constrainOperandRegClass(II, CallReg, 0);
|
|
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(CallReg);
|
|
}
|
|
|
|
// Add implicit physical register uses to the call.
|
|
for (auto Reg : CLI.OutRegs)
|
|
MIB.addReg(Reg, RegState::Implicit);
|
|
|
|
// Add a register mask with the call-preserved registers.
|
|
// Proper defs for return values will be added by setPhysRegsDeadExcept().
|
|
MIB.addRegMask(TRI.getCallPreservedMask(CC));
|
|
|
|
CLI.Call = MIB;
|
|
|
|
// Finish off the call including any return values.
|
|
return FinishCall(CLI, RetVT, NumBytes);
|
|
}
|
|
|
|
bool AArch64FastISel::IsMemCpySmall(uint64_t Len, unsigned Alignment) {
|
|
if (Alignment)
|
|
return Len / Alignment <= 4;
|
|
else
|
|
return Len < 32;
|
|
}
|
|
|
|
bool AArch64FastISel::TryEmitSmallMemCpy(Address Dest, Address Src,
|
|
uint64_t Len, unsigned Alignment) {
|
|
// Make sure we don't bloat code by inlining very large memcpy's.
|
|
if (!IsMemCpySmall(Len, Alignment))
|
|
return false;
|
|
|
|
int64_t UnscaledOffset = 0;
|
|
Address OrigDest = Dest;
|
|
Address OrigSrc = Src;
|
|
|
|
while (Len) {
|
|
MVT VT;
|
|
if (!Alignment || Alignment >= 8) {
|
|
if (Len >= 8)
|
|
VT = MVT::i64;
|
|
else if (Len >= 4)
|
|
VT = MVT::i32;
|
|
else if (Len >= 2)
|
|
VT = MVT::i16;
|
|
else {
|
|
VT = MVT::i8;
|
|
}
|
|
} else {
|
|
// Bound based on alignment.
|
|
if (Len >= 4 && Alignment == 4)
|
|
VT = MVT::i32;
|
|
else if (Len >= 2 && Alignment == 2)
|
|
VT = MVT::i16;
|
|
else {
|
|
VT = MVT::i8;
|
|
}
|
|
}
|
|
|
|
bool RV;
|
|
unsigned ResultReg;
|
|
RV = EmitLoad(VT, ResultReg, Src);
|
|
if (!RV)
|
|
return false;
|
|
|
|
RV = EmitStore(VT, ResultReg, Dest);
|
|
if (!RV)
|
|
return false;
|
|
|
|
int64_t Size = VT.getSizeInBits() / 8;
|
|
Len -= Size;
|
|
UnscaledOffset += Size;
|
|
|
|
// We need to recompute the unscaled offset for each iteration.
|
|
Dest.setOffset(OrigDest.getOffset() + UnscaledOffset);
|
|
Src.setOffset(OrigSrc.getOffset() + UnscaledOffset);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/// \brief Check if it is possible to fold the condition from the XALU intrinsic
|
|
/// into the user. The condition code will only be updated on success.
|
|
bool AArch64FastISel::foldXALUIntrinsic(AArch64CC::CondCode &CC,
|
|
const Instruction *I,
|
|
const Value *Cond) {
|
|
if (!isa<ExtractValueInst>(Cond))
|
|
return false;
|
|
|
|
const auto *EV = cast<ExtractValueInst>(Cond);
|
|
if (!isa<IntrinsicInst>(EV->getAggregateOperand()))
|
|
return false;
|
|
|
|
const auto *II = cast<IntrinsicInst>(EV->getAggregateOperand());
|
|
MVT RetVT;
|
|
const Function *Callee = II->getCalledFunction();
|
|
Type *RetTy =
|
|
cast<StructType>(Callee->getReturnType())->getTypeAtIndex(0U);
|
|
if (!isTypeLegal(RetTy, RetVT))
|
|
return false;
|
|
|
|
if (RetVT != MVT::i32 && RetVT != MVT::i64)
|
|
return false;
|
|
|
|
AArch64CC::CondCode TmpCC;
|
|
switch (II->getIntrinsicID()) {
|
|
default: return false;
|
|
case Intrinsic::sadd_with_overflow:
|
|
case Intrinsic::ssub_with_overflow: TmpCC = AArch64CC::VS; break;
|
|
case Intrinsic::uadd_with_overflow: TmpCC = AArch64CC::HS; break;
|
|
case Intrinsic::usub_with_overflow: TmpCC = AArch64CC::LO; break;
|
|
case Intrinsic::smul_with_overflow:
|
|
case Intrinsic::umul_with_overflow: TmpCC = AArch64CC::NE; break;
|
|
}
|
|
|
|
// Check if both instructions are in the same basic block.
|
|
if (II->getParent() != I->getParent())
|
|
return false;
|
|
|
|
// Make sure nothing is in the way
|
|
BasicBlock::const_iterator Start = I;
|
|
BasicBlock::const_iterator End = II;
|
|
for (auto Itr = std::prev(Start); Itr != End; --Itr) {
|
|
// We only expect extractvalue instructions between the intrinsic and the
|
|
// instruction to be selected.
|
|
if (!isa<ExtractValueInst>(Itr))
|
|
return false;
|
|
|
|
// Check that the extractvalue operand comes from the intrinsic.
|
|
const auto *EVI = cast<ExtractValueInst>(Itr);
|
|
if (EVI->getAggregateOperand() != II)
|
|
return false;
|
|
}
|
|
|
|
CC = TmpCC;
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
|
|
// FIXME: Handle more intrinsics.
|
|
switch (II->getIntrinsicID()) {
|
|
default: return false;
|
|
case Intrinsic::frameaddress: {
|
|
MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
|
|
MFI->setFrameAddressIsTaken(true);
|
|
|
|
const AArch64RegisterInfo *RegInfo =
|
|
static_cast<const AArch64RegisterInfo *>(
|
|
TM.getSubtargetImpl()->getRegisterInfo());
|
|
unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
|
|
unsigned SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(TargetOpcode::COPY), SrcReg).addReg(FramePtr);
|
|
// Recursively load frame address
|
|
// ldr x0, [fp]
|
|
// ldr x0, [x0]
|
|
// ldr x0, [x0]
|
|
// ...
|
|
unsigned DestReg;
|
|
unsigned Depth = cast<ConstantInt>(II->getOperand(0))->getZExtValue();
|
|
while (Depth--) {
|
|
DestReg = FastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass,
|
|
SrcReg, /*IsKill=*/true, 0);
|
|
assert(DestReg && "Unexpected LDR instruction emission failure.");
|
|
SrcReg = DestReg;
|
|
}
|
|
|
|
UpdateValueMap(II, SrcReg);
|
|
return true;
|
|
}
|
|
case Intrinsic::memcpy:
|
|
case Intrinsic::memmove: {
|
|
const auto *MTI = cast<MemTransferInst>(II);
|
|
// Don't handle volatile.
|
|
if (MTI->isVolatile())
|
|
return false;
|
|
|
|
// Disable inlining for memmove before calls to ComputeAddress. Otherwise,
|
|
// we would emit dead code because we don't currently handle memmoves.
|
|
bool IsMemCpy = (II->getIntrinsicID() == Intrinsic::memcpy);
|
|
if (isa<ConstantInt>(MTI->getLength()) && IsMemCpy) {
|
|
// Small memcpy's are common enough that we want to do them without a call
|
|
// if possible.
|
|
uint64_t Len = cast<ConstantInt>(MTI->getLength())->getZExtValue();
|
|
unsigned Alignment = MTI->getAlignment();
|
|
if (IsMemCpySmall(Len, Alignment)) {
|
|
Address Dest, Src;
|
|
if (!ComputeAddress(MTI->getRawDest(), Dest) ||
|
|
!ComputeAddress(MTI->getRawSource(), Src))
|
|
return false;
|
|
if (TryEmitSmallMemCpy(Dest, Src, Len, Alignment))
|
|
return true;
|
|
}
|
|
}
|
|
|
|
if (!MTI->getLength()->getType()->isIntegerTy(64))
|
|
return false;
|
|
|
|
if (MTI->getSourceAddressSpace() > 255 || MTI->getDestAddressSpace() > 255)
|
|
// Fast instruction selection doesn't support the special
|
|
// address spaces.
|
|
return false;
|
|
|
|
const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
|
|
return LowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
|
|
}
|
|
case Intrinsic::memset: {
|
|
const MemSetInst *MSI = cast<MemSetInst>(II);
|
|
// Don't handle volatile.
|
|
if (MSI->isVolatile())
|
|
return false;
|
|
|
|
if (!MSI->getLength()->getType()->isIntegerTy(64))
|
|
return false;
|
|
|
|
if (MSI->getDestAddressSpace() > 255)
|
|
// Fast instruction selection doesn't support the special
|
|
// address spaces.
|
|
return false;
|
|
|
|
return LowerCallTo(II, "memset", II->getNumArgOperands() - 2);
|
|
}
|
|
case Intrinsic::trap: {
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
|
|
.addImm(1);
|
|
return true;
|
|
}
|
|
case Intrinsic::sqrt: {
|
|
Type *RetTy = II->getCalledFunction()->getReturnType();
|
|
|
|
MVT VT;
|
|
if (!isTypeLegal(RetTy, VT))
|
|
return false;
|
|
|
|
unsigned Op0Reg = getRegForValue(II->getOperand(0));
|
|
if (!Op0Reg)
|
|
return false;
|
|
bool Op0IsKill = hasTrivialKill(II->getOperand(0));
|
|
|
|
unsigned ResultReg = FastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);
|
|
if (!ResultReg)
|
|
return false;
|
|
|
|
UpdateValueMap(II, ResultReg);
|
|
return true;
|
|
}
|
|
case Intrinsic::sadd_with_overflow:
|
|
case Intrinsic::uadd_with_overflow:
|
|
case Intrinsic::ssub_with_overflow:
|
|
case Intrinsic::usub_with_overflow:
|
|
case Intrinsic::smul_with_overflow:
|
|
case Intrinsic::umul_with_overflow: {
|
|
// This implements the basic lowering of the xalu with overflow intrinsics.
|
|
const Function *Callee = II->getCalledFunction();
|
|
auto *Ty = cast<StructType>(Callee->getReturnType());
|
|
Type *RetTy = Ty->getTypeAtIndex(0U);
|
|
|
|
MVT VT;
|
|
if (!isTypeLegal(RetTy, VT))
|
|
return false;
|
|
|
|
if (VT != MVT::i32 && VT != MVT::i64)
|
|
return false;
|
|
|
|
const Value *LHS = II->getArgOperand(0);
|
|
const Value *RHS = II->getArgOperand(1);
|
|
// Canonicalize immediate to the RHS.
|
|
if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
|
|
isCommutativeIntrinsic(II))
|
|
std::swap(LHS, RHS);
|
|
|
|
unsigned ResultReg1 = 0, ResultReg2 = 0, MulReg = 0;
|
|
AArch64CC::CondCode CC = AArch64CC::Invalid;
|
|
switch (II->getIntrinsicID()) {
|
|
default: llvm_unreachable("Unexpected intrinsic!");
|
|
case Intrinsic::sadd_with_overflow:
|
|
ResultReg1 = emitAdds(VT, LHS, RHS); CC = AArch64CC::VS; break;
|
|
case Intrinsic::uadd_with_overflow:
|
|
ResultReg1 = emitAdds(VT, LHS, RHS); CC = AArch64CC::HS; break;
|
|
case Intrinsic::ssub_with_overflow:
|
|
ResultReg1 = emitSubs(VT, LHS, RHS); CC = AArch64CC::VS; break;
|
|
case Intrinsic::usub_with_overflow:
|
|
ResultReg1 = emitSubs(VT, LHS, RHS); CC = AArch64CC::LO; break;
|
|
case Intrinsic::smul_with_overflow: {
|
|
CC = AArch64CC::NE;
|
|
unsigned LHSReg = getRegForValue(LHS);
|
|
if (!LHSReg)
|
|
return false;
|
|
bool LHSIsKill = hasTrivialKill(LHS);
|
|
|
|
unsigned RHSReg = getRegForValue(RHS);
|
|
if (!RHSReg)
|
|
return false;
|
|
bool RHSIsKill = hasTrivialKill(RHS);
|
|
|
|
if (VT == MVT::i32) {
|
|
MulReg = Emit_SMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
|
|
unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg,
|
|
/*IsKill=*/false, 32);
|
|
MulReg = FastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
|
|
AArch64::sub_32);
|
|
ShiftReg = FastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true,
|
|
AArch64::sub_32);
|
|
emitSubs_rs(VT, ShiftReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
|
|
AArch64_AM::ASR, 31, /*WantResult=*/false);
|
|
} else {
|
|
assert(VT == MVT::i64 && "Unexpected value type.");
|
|
MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
|
|
unsigned SMULHReg = FastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
|
|
RHSReg, RHSIsKill);
|
|
emitSubs_rs(VT, SMULHReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
|
|
AArch64_AM::ASR, 63, /*WantResult=*/false);
|
|
}
|
|
break;
|
|
}
|
|
case Intrinsic::umul_with_overflow: {
|
|
CC = AArch64CC::NE;
|
|
unsigned LHSReg = getRegForValue(LHS);
|
|
if (!LHSReg)
|
|
return false;
|
|
bool LHSIsKill = hasTrivialKill(LHS);
|
|
|
|
unsigned RHSReg = getRegForValue(RHS);
|
|
if (!RHSReg)
|
|
return false;
|
|
bool RHSIsKill = hasTrivialKill(RHS);
|
|
|
|
if (VT == MVT::i32) {
|
|
MulReg = Emit_UMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
|
|
emitSubs_rs(MVT::i64, AArch64::XZR, /*IsKill=*/true, MulReg,
|
|
/*IsKill=*/false, AArch64_AM::LSR, 32,
|
|
/*WantResult=*/false);
|
|
MulReg = FastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
|
|
AArch64::sub_32);
|
|
} else {
|
|
assert(VT == MVT::i64 && "Unexpected value type.");
|
|
MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
|
|
unsigned UMULHReg = FastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
|
|
RHSReg, RHSIsKill);
|
|
emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg,
|
|
/*IsKill=*/false, /*WantResult=*/false);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (MulReg) {
|
|
ResultReg1 = createResultReg(TLI.getRegClassFor(VT));
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);
|
|
}
|
|
|
|
ResultReg2 = FastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass,
|
|
AArch64::WZR, /*IsKill=*/true, AArch64::WZR,
|
|
/*IsKill=*/true, getInvertedCondCode(CC));
|
|
assert((ResultReg1 + 1) == ResultReg2 &&
|
|
"Nonconsecutive result registers.");
|
|
UpdateValueMap(II, ResultReg1, 2);
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectRet(const Instruction *I) {
|
|
const ReturnInst *Ret = cast<ReturnInst>(I);
|
|
const Function &F = *I->getParent()->getParent();
|
|
|
|
if (!FuncInfo.CanLowerReturn)
|
|
return false;
|
|
|
|
if (F.isVarArg())
|
|
return false;
|
|
|
|
// Build a list of return value registers.
|
|
SmallVector<unsigned, 4> RetRegs;
|
|
|
|
if (Ret->getNumOperands() > 0) {
|
|
CallingConv::ID CC = F.getCallingConv();
|
|
SmallVector<ISD::OutputArg, 4> Outs;
|
|
GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
|
|
|
|
// Analyze operands of the call, assigning locations to each operand.
|
|
SmallVector<CCValAssign, 16> ValLocs;
|
|
CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
|
|
CCAssignFn *RetCC = CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
|
|
: RetCC_AArch64_AAPCS;
|
|
CCInfo.AnalyzeReturn(Outs, RetCC);
|
|
|
|
// Only handle a single return value for now.
|
|
if (ValLocs.size() != 1)
|
|
return false;
|
|
|
|
CCValAssign &VA = ValLocs[0];
|
|
const Value *RV = Ret->getOperand(0);
|
|
|
|
// Don't bother handling odd stuff for now.
|
|
if (VA.getLocInfo() != CCValAssign::Full)
|
|
return false;
|
|
// Only handle register returns for now.
|
|
if (!VA.isRegLoc())
|
|
return false;
|
|
unsigned Reg = getRegForValue(RV);
|
|
if (Reg == 0)
|
|
return false;
|
|
|
|
unsigned SrcReg = Reg + VA.getValNo();
|
|
unsigned DestReg = VA.getLocReg();
|
|
// Avoid a cross-class copy. This is very unlikely.
|
|
if (!MRI.getRegClass(SrcReg)->contains(DestReg))
|
|
return false;
|
|
|
|
EVT RVEVT = TLI.getValueType(RV->getType());
|
|
if (!RVEVT.isSimple())
|
|
return false;
|
|
|
|
// Vectors (of > 1 lane) in big endian need tricky handling.
|
|
if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1)
|
|
return false;
|
|
|
|
MVT RVVT = RVEVT.getSimpleVT();
|
|
if (RVVT == MVT::f128)
|
|
return false;
|
|
MVT DestVT = VA.getValVT();
|
|
// Special handling for extended integers.
|
|
if (RVVT != DestVT) {
|
|
if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
|
|
return false;
|
|
|
|
if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
|
|
return false;
|
|
|
|
bool isZExt = Outs[0].Flags.isZExt();
|
|
SrcReg = EmitIntExt(RVVT, SrcReg, DestVT, isZExt);
|
|
if (SrcReg == 0)
|
|
return false;
|
|
}
|
|
|
|
// Make the copy.
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
|
|
|
|
// Add register to return instruction.
|
|
RetRegs.push_back(VA.getLocReg());
|
|
}
|
|
|
|
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(AArch64::RET_ReallyLR));
|
|
for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
|
|
MIB.addReg(RetRegs[i], RegState::Implicit);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectTrunc(const Instruction *I) {
|
|
Type *DestTy = I->getType();
|
|
Value *Op = I->getOperand(0);
|
|
Type *SrcTy = Op->getType();
|
|
|
|
EVT SrcEVT = TLI.getValueType(SrcTy, true);
|
|
EVT DestEVT = TLI.getValueType(DestTy, true);
|
|
if (!SrcEVT.isSimple())
|
|
return false;
|
|
if (!DestEVT.isSimple())
|
|
return false;
|
|
|
|
MVT SrcVT = SrcEVT.getSimpleVT();
|
|
MVT DestVT = DestEVT.getSimpleVT();
|
|
|
|
if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
|
|
SrcVT != MVT::i8)
|
|
return false;
|
|
if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
|
|
DestVT != MVT::i1)
|
|
return false;
|
|
|
|
unsigned SrcReg = getRegForValue(Op);
|
|
if (!SrcReg)
|
|
return false;
|
|
bool SrcIsKill = hasTrivialKill(Op);
|
|
|
|
// If we're truncating from i64 to a smaller non-legal type then generate an
|
|
// AND. Otherwise, we know the high bits are undefined and a truncate only
|
|
// generate a COPY. We cannot mark the source register also as result
|
|
// register, because this can incorrectly transfer the kill flag onto the
|
|
// source register.
|
|
unsigned ResultReg;
|
|
if (SrcVT == MVT::i64) {
|
|
uint64_t Mask = 0;
|
|
switch (DestVT.SimpleTy) {
|
|
default:
|
|
// Trunc i64 to i32 is handled by the target-independent fast-isel.
|
|
return false;
|
|
case MVT::i1:
|
|
Mask = 0x1;
|
|
break;
|
|
case MVT::i8:
|
|
Mask = 0xff;
|
|
break;
|
|
case MVT::i16:
|
|
Mask = 0xffff;
|
|
break;
|
|
}
|
|
// Issue an extract_subreg to get the lower 32-bits.
|
|
unsigned Reg32 = FastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
|
|
AArch64::sub_32);
|
|
// Create the AND instruction which performs the actual truncation.
|
|
ResultReg = emitAND_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
|
|
assert(ResultReg && "Unexpected AND instruction emission failure.");
|
|
} else {
|
|
ResultReg = createResultReg(&AArch64::GPR32RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(TargetOpcode::COPY), ResultReg)
|
|
.addReg(SrcReg, getKillRegState(SrcIsKill));
|
|
}
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
|
|
assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
|
|
DestVT == MVT::i64) &&
|
|
"Unexpected value type.");
|
|
// Handle i8 and i16 as i32.
|
|
if (DestVT == MVT::i8 || DestVT == MVT::i16)
|
|
DestVT = MVT::i32;
|
|
|
|
if (isZExt) {
|
|
unsigned ResultReg = emitAND_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
|
|
assert(ResultReg && "Unexpected AND instruction emission failure.");
|
|
if (DestVT == MVT::i64) {
|
|
// We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
|
|
// upper 32 bits. Emit a SUBREG_TO_REG to extend from Wd to Xd.
|
|
unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(AArch64::SUBREG_TO_REG), Reg64)
|
|
.addImm(0)
|
|
.addReg(ResultReg)
|
|
.addImm(AArch64::sub_32);
|
|
ResultReg = Reg64;
|
|
}
|
|
return ResultReg;
|
|
} else {
|
|
if (DestVT == MVT::i64) {
|
|
// FIXME: We're SExt i1 to i64.
|
|
return 0;
|
|
}
|
|
return FastEmitInst_rii(AArch64::SBFMWri, &AArch64::GPR32RegClass, SrcReg,
|
|
/*TODO:IsKill=*/false, 0, 0);
|
|
}
|
|
}
|
|
|
|
unsigned AArch64FastISel::Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
|
unsigned Op1, bool Op1IsKill) {
|
|
unsigned Opc, ZReg;
|
|
switch (RetVT.SimpleTy) {
|
|
default: return 0;
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
RetVT = MVT::i32;
|
|
Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break;
|
|
case MVT::i64:
|
|
Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break;
|
|
}
|
|
|
|
const TargetRegisterClass *RC =
|
|
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
return FastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill,
|
|
/*IsKill=*/ZReg, true);
|
|
}
|
|
|
|
unsigned AArch64FastISel::Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
|
unsigned Op1, bool Op1IsKill) {
|
|
if (RetVT != MVT::i64)
|
|
return 0;
|
|
|
|
return FastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass,
|
|
Op0, Op0IsKill, Op1, Op1IsKill,
|
|
AArch64::XZR, /*IsKill=*/true);
|
|
}
|
|
|
|
unsigned AArch64FastISel::Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
|
unsigned Op1, bool Op1IsKill) {
|
|
if (RetVT != MVT::i64)
|
|
return 0;
|
|
|
|
return FastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass,
|
|
Op0, Op0IsKill, Op1, Op1IsKill,
|
|
AArch64::XZR, /*IsKill=*/true);
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
|
|
unsigned Op1Reg, bool Op1IsKill) {
|
|
unsigned Opc = 0;
|
|
bool NeedTrunc = false;
|
|
uint64_t Mask = 0;
|
|
switch (RetVT.SimpleTy) {
|
|
default: return 0;
|
|
case MVT::i8: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xff; break;
|
|
case MVT::i16: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xffff; break;
|
|
case MVT::i32: Opc = AArch64::LSLVWr; break;
|
|
case MVT::i64: Opc = AArch64::LSLVXr; break;
|
|
}
|
|
|
|
const TargetRegisterClass *RC =
|
|
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
if (NeedTrunc) {
|
|
Op1Reg = emitAND_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
|
|
Op1IsKill = true;
|
|
}
|
|
unsigned ResultReg = FastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
|
|
Op1IsKill);
|
|
if (NeedTrunc)
|
|
ResultReg = emitAND_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
|
|
bool Op0IsKill, uint64_t Shift,
|
|
bool IsZext) {
|
|
assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
|
|
"Unexpected source/return type pair.");
|
|
assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
|
|
SrcVT == MVT::i64) && "Unexpected source value type.");
|
|
assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
|
|
RetVT == MVT::i64) && "Unexpected return value type.");
|
|
|
|
bool Is64Bit = (RetVT == MVT::i64);
|
|
unsigned RegSize = Is64Bit ? 64 : 32;
|
|
unsigned DstBits = RetVT.getSizeInBits();
|
|
unsigned SrcBits = SrcVT.getSizeInBits();
|
|
|
|
// Don't deal with undefined shifts.
|
|
if (Shift >= DstBits)
|
|
return 0;
|
|
|
|
// For immediate shifts we can fold the zero-/sign-extension into the shift.
|
|
// {S|U}BFM Wd, Wn, #r, #s
|
|
// Wd<32+s-r,32-r> = Wn<s:0> when r > s
|
|
|
|
// %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
|
|
// %2 = shl i16 %1, 4
|
|
// Wd<32+7-28,32-28> = Wn<7:0> <- clamp s to 7
|
|
// 0b1111_1111_1111_1111__1111_1010_1010_0000 sext
|
|
// 0b0000_0000_0000_0000__0000_0101_0101_0000 sext | zext
|
|
// 0b0000_0000_0000_0000__0000_1010_1010_0000 zext
|
|
|
|
// %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
|
|
// %2 = shl i16 %1, 8
|
|
// Wd<32+7-24,32-24> = Wn<7:0>
|
|
// 0b1111_1111_1111_1111__1010_1010_0000_0000 sext
|
|
// 0b0000_0000_0000_0000__0101_0101_0000_0000 sext | zext
|
|
// 0b0000_0000_0000_0000__1010_1010_0000_0000 zext
|
|
|
|
// %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
|
|
// %2 = shl i16 %1, 12
|
|
// Wd<32+3-20,32-20> = Wn<3:0>
|
|
// 0b1111_1111_1111_1111__1010_0000_0000_0000 sext
|
|
// 0b0000_0000_0000_0000__0101_0000_0000_0000 sext | zext
|
|
// 0b0000_0000_0000_0000__1010_0000_0000_0000 zext
|
|
|
|
unsigned ImmR = RegSize - Shift;
|
|
// Limit the width to the length of the source type.
|
|
unsigned ImmS = std::min<unsigned>(SrcBits - 1, DstBits - 1 - Shift);
|
|
static const unsigned OpcTable[2][2] = {
|
|
{AArch64::SBFMWri, AArch64::SBFMXri},
|
|
{AArch64::UBFMWri, AArch64::UBFMXri}
|
|
};
|
|
unsigned Opc = OpcTable[IsZext][Is64Bit];
|
|
const TargetRegisterClass *RC =
|
|
Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
|
|
unsigned TmpReg = MRI.createVirtualRegister(RC);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(AArch64::SUBREG_TO_REG), TmpReg)
|
|
.addImm(0)
|
|
.addReg(Op0, getKillRegState(Op0IsKill))
|
|
.addImm(AArch64::sub_32);
|
|
Op0 = TmpReg;
|
|
Op0IsKill = true;
|
|
}
|
|
return FastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
|
|
unsigned Op1Reg, bool Op1IsKill) {
|
|
unsigned Opc = 0;
|
|
bool NeedTrunc = false;
|
|
uint64_t Mask = 0;
|
|
switch (RetVT.SimpleTy) {
|
|
default: return 0;
|
|
case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break;
|
|
case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break;
|
|
case MVT::i32: Opc = AArch64::LSRVWr; break;
|
|
case MVT::i64: Opc = AArch64::LSRVXr; break;
|
|
}
|
|
|
|
const TargetRegisterClass *RC =
|
|
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
if (NeedTrunc) {
|
|
Op0Reg = emitAND_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);
|
|
Op1Reg = emitAND_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
|
|
Op0IsKill = Op1IsKill = true;
|
|
}
|
|
unsigned ResultReg = FastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
|
|
Op1IsKill);
|
|
if (NeedTrunc)
|
|
ResultReg = emitAND_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
|
|
bool Op0IsKill, uint64_t Shift,
|
|
bool IsZExt) {
|
|
assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
|
|
"Unexpected source/return type pair.");
|
|
assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
|
|
SrcVT == MVT::i64) && "Unexpected source value type.");
|
|
assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
|
|
RetVT == MVT::i64) && "Unexpected return value type.");
|
|
|
|
bool Is64Bit = (RetVT == MVT::i64);
|
|
unsigned RegSize = Is64Bit ? 64 : 32;
|
|
unsigned DstBits = RetVT.getSizeInBits();
|
|
unsigned SrcBits = SrcVT.getSizeInBits();
|
|
|
|
// Don't deal with undefined shifts.
|
|
if (Shift >= DstBits)
|
|
return 0;
|
|
|
|
// For immediate shifts we can fold the zero-/sign-extension into the shift.
|
|
// {S|U}BFM Wd, Wn, #r, #s
|
|
// Wd<s-r:0> = Wn<s:r> when r <= s
|
|
|
|
// %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
|
|
// %2 = lshr i16 %1, 4
|
|
// Wd<7-4:0> = Wn<7:4>
|
|
// 0b0000_0000_0000_0000__0000_1111_1111_1010 sext
|
|
// 0b0000_0000_0000_0000__0000_0000_0000_0101 sext | zext
|
|
// 0b0000_0000_0000_0000__0000_0000_0000_1010 zext
|
|
|
|
// %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
|
|
// %2 = lshr i16 %1, 8
|
|
// Wd<7-7,0> = Wn<7:7>
|
|
// 0b0000_0000_0000_0000__0000_0000_1111_1111 sext
|
|
// 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
|
|
// 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
|
|
|
|
// %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
|
|
// %2 = lshr i16 %1, 12
|
|
// Wd<7-7,0> = Wn<7:7> <- clamp r to 7
|
|
// 0b0000_0000_0000_0000__0000_0000_0000_1111 sext
|
|
// 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
|
|
// 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
|
|
|
|
if (Shift >= SrcBits && IsZExt)
|
|
return AArch64MaterializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)),
|
|
RetVT);
|
|
|
|
// It is not possible to fold a sign-extend into the LShr instruction. In this
|
|
// case emit a sign-extend.
|
|
if (!IsZExt) {
|
|
Op0 = EmitIntExt(SrcVT, Op0, RetVT, IsZExt);
|
|
if (!Op0)
|
|
return 0;
|
|
Op0IsKill = true;
|
|
SrcVT = RetVT;
|
|
SrcBits = SrcVT.getSizeInBits();
|
|
IsZExt = true;
|
|
}
|
|
|
|
unsigned ImmR = std::min<unsigned>(SrcBits - 1, Shift);
|
|
unsigned ImmS = SrcBits - 1;
|
|
static const unsigned OpcTable[2][2] = {
|
|
{AArch64::SBFMWri, AArch64::SBFMXri},
|
|
{AArch64::UBFMWri, AArch64::UBFMXri}
|
|
};
|
|
unsigned Opc = OpcTable[IsZExt][Is64Bit];
|
|
const TargetRegisterClass *RC =
|
|
Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
|
|
unsigned TmpReg = MRI.createVirtualRegister(RC);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(AArch64::SUBREG_TO_REG), TmpReg)
|
|
.addImm(0)
|
|
.addReg(Op0, getKillRegState(Op0IsKill))
|
|
.addImm(AArch64::sub_32);
|
|
Op0 = TmpReg;
|
|
Op0IsKill = true;
|
|
}
|
|
return FastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
|
|
unsigned Op1Reg, bool Op1IsKill) {
|
|
unsigned Opc = 0;
|
|
bool NeedTrunc = false;
|
|
uint64_t Mask = 0;
|
|
switch (RetVT.SimpleTy) {
|
|
default: return 0;
|
|
case MVT::i8: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xff; break;
|
|
case MVT::i16: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xffff; break;
|
|
case MVT::i32: Opc = AArch64::ASRVWr; break;
|
|
case MVT::i64: Opc = AArch64::ASRVXr; break;
|
|
}
|
|
|
|
const TargetRegisterClass *RC =
|
|
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
if (NeedTrunc) {
|
|
Op0Reg = EmitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false);
|
|
Op1Reg = emitAND_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
|
|
Op0IsKill = Op1IsKill = true;
|
|
}
|
|
unsigned ResultReg = FastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
|
|
Op1IsKill);
|
|
if (NeedTrunc)
|
|
ResultReg = emitAND_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
|
|
return ResultReg;
|
|
}
|
|
|
|
unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
|
|
bool Op0IsKill, uint64_t Shift,
|
|
bool IsZExt) {
|
|
assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
|
|
"Unexpected source/return type pair.");
|
|
assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
|
|
SrcVT == MVT::i64) && "Unexpected source value type.");
|
|
assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
|
|
RetVT == MVT::i64) && "Unexpected return value type.");
|
|
|
|
bool Is64Bit = (RetVT == MVT::i64);
|
|
unsigned RegSize = Is64Bit ? 64 : 32;
|
|
unsigned DstBits = RetVT.getSizeInBits();
|
|
unsigned SrcBits = SrcVT.getSizeInBits();
|
|
|
|
// Don't deal with undefined shifts.
|
|
if (Shift >= DstBits)
|
|
return 0;
|
|
|
|
// For immediate shifts we can fold the zero-/sign-extension into the shift.
|
|
// {S|U}BFM Wd, Wn, #r, #s
|
|
// Wd<s-r:0> = Wn<s:r> when r <= s
|
|
|
|
// %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
|
|
// %2 = ashr i16 %1, 4
|
|
// Wd<7-4:0> = Wn<7:4>
|
|
// 0b1111_1111_1111_1111__1111_1111_1111_1010 sext
|
|
// 0b0000_0000_0000_0000__0000_0000_0000_0101 sext | zext
|
|
// 0b0000_0000_0000_0000__0000_0000_0000_1010 zext
|
|
|
|
// %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
|
|
// %2 = ashr i16 %1, 8
|
|
// Wd<7-7,0> = Wn<7:7>
|
|
// 0b1111_1111_1111_1111__1111_1111_1111_1111 sext
|
|
// 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
|
|
// 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
|
|
|
|
// %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
|
|
// %2 = ashr i16 %1, 12
|
|
// Wd<7-7,0> = Wn<7:7> <- clamp r to 7
|
|
// 0b1111_1111_1111_1111__1111_1111_1111_1111 sext
|
|
// 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
|
|
// 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
|
|
|
|
if (Shift >= SrcBits && IsZExt)
|
|
return AArch64MaterializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)),
|
|
RetVT);
|
|
|
|
unsigned ImmR = std::min<unsigned>(SrcBits - 1, Shift);
|
|
unsigned ImmS = SrcBits - 1;
|
|
static const unsigned OpcTable[2][2] = {
|
|
{AArch64::SBFMWri, AArch64::SBFMXri},
|
|
{AArch64::UBFMWri, AArch64::UBFMXri}
|
|
};
|
|
unsigned Opc = OpcTable[IsZExt][Is64Bit];
|
|
const TargetRegisterClass *RC =
|
|
Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
|
|
unsigned TmpReg = MRI.createVirtualRegister(RC);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(AArch64::SUBREG_TO_REG), TmpReg)
|
|
.addImm(0)
|
|
.addReg(Op0, getKillRegState(Op0IsKill))
|
|
.addImm(AArch64::sub_32);
|
|
Op0 = TmpReg;
|
|
Op0IsKill = true;
|
|
}
|
|
return FastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
|
|
}
|
|
|
|
unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
|
bool isZExt) {
|
|
assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
|
|
|
|
// FastISel does not have plumbing to deal with extensions where the SrcVT or
|
|
// DestVT are odd things, so test to make sure that they are both types we can
|
|
// handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
|
|
// bail out to SelectionDAG.
|
|
if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
|
|
(DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
|
|
((SrcVT != MVT::i1) && (SrcVT != MVT::i8) &&
|
|
(SrcVT != MVT::i16) && (SrcVT != MVT::i32)))
|
|
return 0;
|
|
|
|
unsigned Opc;
|
|
unsigned Imm = 0;
|
|
|
|
switch (SrcVT.SimpleTy) {
|
|
default:
|
|
return 0;
|
|
case MVT::i1:
|
|
return Emiti1Ext(SrcReg, DestVT, isZExt);
|
|
case MVT::i8:
|
|
if (DestVT == MVT::i64)
|
|
Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
|
|
else
|
|
Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
|
|
Imm = 7;
|
|
break;
|
|
case MVT::i16:
|
|
if (DestVT == MVT::i64)
|
|
Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
|
|
else
|
|
Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
|
|
Imm = 15;
|
|
break;
|
|
case MVT::i32:
|
|
assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
|
|
Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
|
|
Imm = 31;
|
|
break;
|
|
}
|
|
|
|
// Handle i8 and i16 as i32.
|
|
if (DestVT == MVT::i8 || DestVT == MVT::i16)
|
|
DestVT = MVT::i32;
|
|
else if (DestVT == MVT::i64) {
|
|
unsigned Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(AArch64::SUBREG_TO_REG), Src64)
|
|
.addImm(0)
|
|
.addReg(SrcReg)
|
|
.addImm(AArch64::sub_32);
|
|
SrcReg = Src64;
|
|
}
|
|
|
|
const TargetRegisterClass *RC =
|
|
(DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
return FastEmitInst_rii(Opc, RC, SrcReg, /*TODO:IsKill=*/false, 0, Imm);
|
|
}
|
|
|
|
bool AArch64FastISel::SelectIntExt(const Instruction *I) {
|
|
// On ARM, in general, integer casts don't involve legal types; this code
|
|
// handles promotable integers. The high bits for a type smaller than
|
|
// the register size are assumed to be undefined.
|
|
Type *DestTy = I->getType();
|
|
Value *Src = I->getOperand(0);
|
|
Type *SrcTy = Src->getType();
|
|
|
|
bool isZExt = isa<ZExtInst>(I);
|
|
unsigned SrcReg = getRegForValue(Src);
|
|
if (!SrcReg)
|
|
return false;
|
|
|
|
EVT SrcEVT = TLI.getValueType(SrcTy, true);
|
|
EVT DestEVT = TLI.getValueType(DestTy, true);
|
|
if (!SrcEVT.isSimple())
|
|
return false;
|
|
if (!DestEVT.isSimple())
|
|
return false;
|
|
|
|
MVT SrcVT = SrcEVT.getSimpleVT();
|
|
MVT DestVT = DestEVT.getSimpleVT();
|
|
unsigned ResultReg = 0;
|
|
|
|
// Check if it is an argument and if it is already zero/sign-extended.
|
|
if (const auto *Arg = dyn_cast<Argument>(Src)) {
|
|
if ((isZExt && Arg->hasZExtAttr()) || (!isZExt && Arg->hasSExtAttr())) {
|
|
if (DestVT == MVT::i64) {
|
|
ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
TII.get(AArch64::SUBREG_TO_REG), ResultReg)
|
|
.addImm(0)
|
|
.addReg(SrcReg)
|
|
.addImm(AArch64::sub_32);
|
|
} else
|
|
ResultReg = SrcReg;
|
|
}
|
|
}
|
|
|
|
if (!ResultReg)
|
|
ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
|
|
|
|
if (!ResultReg)
|
|
return false;
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
|
|
EVT DestEVT = TLI.getValueType(I->getType(), true);
|
|
if (!DestEVT.isSimple())
|
|
return false;
|
|
|
|
MVT DestVT = DestEVT.getSimpleVT();
|
|
if (DestVT != MVT::i64 && DestVT != MVT::i32)
|
|
return false;
|
|
|
|
unsigned DivOpc;
|
|
bool is64bit = (DestVT == MVT::i64);
|
|
switch (ISDOpcode) {
|
|
default:
|
|
return false;
|
|
case ISD::SREM:
|
|
DivOpc = is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
|
|
break;
|
|
case ISD::UREM:
|
|
DivOpc = is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
|
|
break;
|
|
}
|
|
unsigned MSubOpc = is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
|
|
unsigned Src0Reg = getRegForValue(I->getOperand(0));
|
|
if (!Src0Reg)
|
|
return false;
|
|
bool Src0IsKill = hasTrivialKill(I->getOperand(0));
|
|
|
|
unsigned Src1Reg = getRegForValue(I->getOperand(1));
|
|
if (!Src1Reg)
|
|
return false;
|
|
bool Src1IsKill = hasTrivialKill(I->getOperand(1));
|
|
|
|
const TargetRegisterClass *RC =
|
|
(DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
|
unsigned QuotReg = FastEmitInst_rr(DivOpc, RC, Src0Reg, /*IsKill=*/false,
|
|
Src1Reg, /*IsKill=*/false);
|
|
assert(QuotReg && "Unexpected DIV instruction emission failure.");
|
|
// The remainder is computed as numerator - (quotient * denominator) using the
|
|
// MSUB instruction.
|
|
unsigned ResultReg = FastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true,
|
|
Src1Reg, Src1IsKill, Src0Reg,
|
|
Src0IsKill);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectMul(const Instruction *I) {
|
|
EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType(), true);
|
|
if (!SrcEVT.isSimple())
|
|
return false;
|
|
MVT SrcVT = SrcEVT.getSimpleVT();
|
|
|
|
// Must be simple value type. Don't handle vectors.
|
|
if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
|
|
SrcVT != MVT::i8)
|
|
return false;
|
|
|
|
unsigned Src0Reg = getRegForValue(I->getOperand(0));
|
|
if (!Src0Reg)
|
|
return false;
|
|
bool Src0IsKill = hasTrivialKill(I->getOperand(0));
|
|
|
|
unsigned Src1Reg = getRegForValue(I->getOperand(1));
|
|
if (!Src1Reg)
|
|
return false;
|
|
bool Src1IsKill = hasTrivialKill(I->getOperand(1));
|
|
|
|
unsigned ResultReg =
|
|
Emit_MUL_rr(SrcVT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
|
|
|
|
if (!ResultReg)
|
|
return false;
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectShift(const Instruction *I) {
|
|
MVT RetVT;
|
|
if (!isLoadStoreTypeLegal(I->getType(), RetVT))
|
|
return false;
|
|
|
|
if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
|
|
unsigned ResultReg = 0;
|
|
uint64_t ShiftVal = C->getZExtValue();
|
|
MVT SrcVT = RetVT;
|
|
bool IsZExt = (I->getOpcode() == Instruction::AShr) ? false : true;
|
|
const Value *Op0 = I->getOperand(0);
|
|
if (const auto *ZExt = dyn_cast<ZExtInst>(Op0)) {
|
|
MVT TmpVT;
|
|
if (isValueAvailable(ZExt) &&
|
|
isLoadStoreTypeLegal(ZExt->getSrcTy(), TmpVT)) {
|
|
SrcVT = TmpVT;
|
|
IsZExt = true;
|
|
Op0 = ZExt->getOperand(0);
|
|
}
|
|
} else if (const auto *SExt = dyn_cast<SExtInst>(Op0)) {
|
|
MVT TmpVT;
|
|
if (isValueAvailable(SExt) &&
|
|
isLoadStoreTypeLegal(SExt->getSrcTy(), TmpVT)) {
|
|
SrcVT = TmpVT;
|
|
IsZExt = false;
|
|
Op0 = SExt->getOperand(0);
|
|
}
|
|
}
|
|
|
|
unsigned Op0Reg = getRegForValue(Op0);
|
|
if (!Op0Reg)
|
|
return false;
|
|
bool Op0IsKill = hasTrivialKill(Op0);
|
|
|
|
switch (I->getOpcode()) {
|
|
default: llvm_unreachable("Unexpected instruction.");
|
|
case Instruction::Shl:
|
|
ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
|
|
break;
|
|
case Instruction::AShr:
|
|
ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
|
|
break;
|
|
case Instruction::LShr:
|
|
ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
|
|
break;
|
|
}
|
|
if (!ResultReg)
|
|
return false;
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
unsigned Op0Reg = getRegForValue(I->getOperand(0));
|
|
if (!Op0Reg)
|
|
return false;
|
|
bool Op0IsKill = hasTrivialKill(I->getOperand(0));
|
|
|
|
unsigned Op1Reg = getRegForValue(I->getOperand(1));
|
|
if (!Op1Reg)
|
|
return false;
|
|
bool Op1IsKill = hasTrivialKill(I->getOperand(1));
|
|
|
|
unsigned ResultReg = 0;
|
|
switch (I->getOpcode()) {
|
|
default: llvm_unreachable("Unexpected instruction.");
|
|
case Instruction::Shl:
|
|
ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
|
|
break;
|
|
case Instruction::AShr:
|
|
ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
|
|
break;
|
|
case Instruction::LShr:
|
|
ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
|
|
break;
|
|
}
|
|
|
|
if (!ResultReg)
|
|
return false;
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::SelectBitCast(const Instruction *I) {
|
|
MVT RetVT, SrcVT;
|
|
|
|
if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))
|
|
return false;
|
|
if (!isTypeLegal(I->getType(), RetVT))
|
|
return false;
|
|
|
|
unsigned Opc;
|
|
if (RetVT == MVT::f32 && SrcVT == MVT::i32)
|
|
Opc = AArch64::FMOVWSr;
|
|
else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
|
|
Opc = AArch64::FMOVXDr;
|
|
else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
|
|
Opc = AArch64::FMOVSWr;
|
|
else if (RetVT == MVT::i64 && SrcVT == MVT::f64)
|
|
Opc = AArch64::FMOVDXr;
|
|
else
|
|
return false;
|
|
|
|
const TargetRegisterClass *RC = nullptr;
|
|
switch (RetVT.SimpleTy) {
|
|
default: llvm_unreachable("Unexpected value type.");
|
|
case MVT::i32: RC = &AArch64::GPR32RegClass; break;
|
|
case MVT::i64: RC = &AArch64::GPR64RegClass; break;
|
|
case MVT::f32: RC = &AArch64::FPR32RegClass; break;
|
|
case MVT::f64: RC = &AArch64::FPR64RegClass; break;
|
|
}
|
|
unsigned Op0Reg = getRegForValue(I->getOperand(0));
|
|
if (!Op0Reg)
|
|
return false;
|
|
bool Op0IsKill = hasTrivialKill(I->getOperand(0));
|
|
unsigned ResultReg = FastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);
|
|
|
|
if (!ResultReg)
|
|
return false;
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FastISel::TargetSelectInstruction(const Instruction *I) {
|
|
switch (I->getOpcode()) {
|
|
default:
|
|
break;
|
|
case Instruction::Load:
|
|
return SelectLoad(I);
|
|
case Instruction::Store:
|
|
return SelectStore(I);
|
|
case Instruction::Br:
|
|
return SelectBranch(I);
|
|
case Instruction::IndirectBr:
|
|
return SelectIndirectBr(I);
|
|
case Instruction::FCmp:
|
|
case Instruction::ICmp:
|
|
return SelectCmp(I);
|
|
case Instruction::Select:
|
|
return SelectSelect(I);
|
|
case Instruction::FPExt:
|
|
return SelectFPExt(I);
|
|
case Instruction::FPTrunc:
|
|
return SelectFPTrunc(I);
|
|
case Instruction::FPToSI:
|
|
return SelectFPToInt(I, /*Signed=*/true);
|
|
case Instruction::FPToUI:
|
|
return SelectFPToInt(I, /*Signed=*/false);
|
|
case Instruction::SIToFP:
|
|
return SelectIntToFP(I, /*Signed=*/true);
|
|
case Instruction::UIToFP:
|
|
return SelectIntToFP(I, /*Signed=*/false);
|
|
case Instruction::SRem:
|
|
return SelectRem(I, ISD::SREM);
|
|
case Instruction::URem:
|
|
return SelectRem(I, ISD::UREM);
|
|
case Instruction::Ret:
|
|
return SelectRet(I);
|
|
case Instruction::Trunc:
|
|
return SelectTrunc(I);
|
|
case Instruction::ZExt:
|
|
case Instruction::SExt:
|
|
return SelectIntExt(I);
|
|
|
|
// FIXME: All of these should really be handled by the target-independent
|
|
// selector -> improve FastISel tblgen.
|
|
case Instruction::Mul:
|
|
return SelectMul(I);
|
|
case Instruction::Shl: // fall-through
|
|
case Instruction::LShr: // fall-through
|
|
case Instruction::AShr:
|
|
return SelectShift(I);
|
|
case Instruction::BitCast:
|
|
return SelectBitCast(I);
|
|
}
|
|
return false;
|
|
// Silence warnings.
|
|
(void)&CC_AArch64_DarwinPCS_VarArg;
|
|
}
|
|
|
|
namespace llvm {
|
|
llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo) {
|
|
return new AArch64FastISel(funcInfo, libInfo);
|
|
}
|
|
}
|